drm/amdgpu: add structures for umc error address translation

add related registers, callback function and channel index table

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index f5d6def..dfa1a39 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -24,6 +24,8 @@
 struct amdgpu_umc_funcs {
        void (*query_ras_error_count)(struct amdgpu_device *adev,
                                        void *ras_error_status);
+       void (*query_ras_error_address)(struct amdgpu_device *adev,
+                                       void *ras_error_status);
 };
 
 struct amdgpu_umc {

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 5b1ccb8..e05f3e6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -29,6 +29,16 @@
 #include "umc/umc_6_1_1_offset.h"
 #include "umc/umc_6_1_1_sh_mask.h"
 
+#define smnMCA_UMC0_MCUMC_ADDRT0       0x50f10
+
+static uint32_t
+       umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
+               {2, 18, 11, 27},        {4, 20, 13, 29},
+               {1, 17, 8, 24},         {7, 23, 14, 30},
+               {10, 26, 3, 19},        {12, 28, 5, 21},
+               {9, 25, 0, 16},         {15, 31, 6, 22}
+};
+
 static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
                                           uint32_t umc_instance)
 {