drm/i915: fix whitelist selftests with readonly registers
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Sat, 29 Jun 2019 13:13:50 +0000 (14:13 +0100)
committerJani Nikula <jani.nikula@intel.com>
Mon, 29 Jul 2019 12:28:21 +0000 (15:28 +0300)
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :

   KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

v2: Use a local to shrink under 80cols.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context registers")
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190629131350.31185-1-chris@chris-wilson.co.uk
(cherry picked from commit 361b69051326ed0e07553315227678d00d651a9e)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gt/selftest_workarounds.c

index 9eaf030..44becd9 100644 (file)
@@ -925,7 +925,12 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
 
        err = 0;
        for (i = 0; i < engine->whitelist.count; i++) {
-               if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
+               const struct i915_wa *wa = &engine->whitelist.list[i];
+
+               if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
+                       continue;
+
+               if (!fn(engine, a[i], b[i], wa->reg))
                        err = -EINVAL;
        }