Mark widenable condition as noundef

This corresponds to its description in LangRef:
The intrinsic @llvm.experimental.widenable.condition() returns either true or false.

Differential Revision: https://reviews.llvm.org/D146508
Reviewed By: skatkov, nikic

diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 0e32ca9..c24f53c 100644 (file)
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1376,7 +1376,7 @@ def int_experimental_guard : DefaultAttrsIntrinsic<[], [llvm_i1_ty, llvm_vararg_
 
 // Supports widenable conditions for guards represented as explicit branches.
 def int_experimental_widenable_condition : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
-        [IntrInaccessibleMemOnly, IntrWillReturn, IntrSpeculatable]>;
+        [IntrInaccessibleMemOnly, IntrWillReturn, IntrSpeculatable, NoUndef<RetIndex>]>;
 
 // NOP: calls/invokes to this intrinsic are removed by codegen
 def int_donothing : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrWillReturn]>;

diff --git a/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll b/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
index 1d8d2a8..105bd28 100644 (file)
--- a/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
@@ -419,8 +419,7 @@ define <vscale x 2 x i32> @sshl_sat_v2i32_scalable_zeroinitializer(<vscale x 2 x
 define i1 @widenable_condition() {
 ; CHECK-LABEL: @widenable_condition(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[FREEZE:%.*]] = freeze i1 [[WC]]
-; CHECK-NEXT:    ret i1 [[FREEZE]]
+; CHECK-NEXT:    ret i1 [[WC]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %freeze = freeze i1 %wc

diff --git a/llvm/test/Transforms/InstCombine/widenable-conditions.ll b/llvm/test/Transforms/InstCombine/widenable-conditions.ll
index df00fba..0e377c9 100644 (file)
--- a/llvm/test/Transforms/InstCombine/widenable-conditions.ll
+++ b/llvm/test/Transforms/InstCombine/widenable-conditions.ll
@@ -20,7 +20,7 @@ define i1 @test1(i1 %a, i1 %b) {
 define i1 @test1_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
@@ -49,7 +49,7 @@ define i1 @test1b(i1 %a, i1 %b) {
 define i1 @test1b_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1b_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B:%.*]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
 ; CHECK-NEXT:    call void @use(i1 [[LHS]])
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
@@ -87,7 +87,7 @@ define i1 @test1c_logical(i1 %a, i1 %b) {
 ; CHECK-NEXT:    call void @use(i1 [[B:%.*]])
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC]])
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[B]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[LHS:%.*]] = and i1 [[WC]], [[B]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[A]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
@@ -147,8 +147,8 @@ define i1 @test3_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test3_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[LHS]], i1 [[RHS]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
@@ -177,7 +177,7 @@ define i1 @test4_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test4_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[LHS]], i1 [[WC]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[LHS]], [[WC]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
@@ -225,7 +225,7 @@ define i1 @test6_logical(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test6_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
@@ -254,7 +254,7 @@ define i1 @test7_logical(i1 %a, i1 %b) {
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC]])
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
@@ -284,7 +284,7 @@ define i1 @test8_logical(i1 %a, i1 %b) {
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    call void @use(i1 [[WC2]])
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[WC]], i1 [[WC2]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[WC]], [[WC2]]
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()

diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll b/llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll
index 16255cb..0964c55 100644 (file)
--- a/llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll
+++ b/llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll
@@ -7,10 +7,11 @@ define void @test() {
 ; CHECK-NEXT:    [[TMP:%.*]] = call i1 @llvm.experimental.widenable.condition()
 ; CHECK-NEXT:    [[TMP1:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
 ; CHECK-NEXT:    [[TMP2:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
+; CHECK-NEXT:    br i1 [[TMP]], label [[BB_SPLIT:%.*]], label [[BB3_SPLIT_US:%.*]]
+; CHECK:       bb.split:
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[TMP_FR:%.*]] = freeze i1 [[TMP]]
-; CHECK-NEXT:    br i1 [[TMP_FR]], label [[BB3_SPLIT:%.*]], label [[BB3_SPLIT_US:%.*]]
+; CHECK-NEXT:    br label [[BB3_SPLIT:%.*]]
 ; CHECK:       bb3.split.us:
 ; CHECK-NEXT:    br label [[BB4_US:%.*]]
 ; CHECK:       bb4.us: