clk: renesas: r8a779f0: Fix HSCIF parent clocks

As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.

Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.

Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index e4f2bbb..fd14624 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -128,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
-       DEF_MOD("hscif0",       514,    R8A779F0_CLK_S0D3),
-       DEF_MOD("hscif1",       515,    R8A779F0_CLK_S0D3),
-       DEF_MOD("hscif2",       516,    R8A779F0_CLK_S0D3),
-       DEF_MOD("hscif3",       517,    R8A779F0_CLK_S0D3),
+       DEF_MOD("hscif0",       514,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif1",       515,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif2",       516,    R8A779F0_CLK_SASYNCPERD1),
+       DEF_MOD("hscif3",       517,    R8A779F0_CLK_SASYNCPERD1),
        DEF_MOD("i2c0",         518,    R8A779F0_CLK_S0D6_PER),
        DEF_MOD("i2c1",         519,    R8A779F0_CLK_S0D6_PER),
        DEF_MOD("i2c2",         520,    R8A779F0_CLK_S0D6_PER),