* 50/50:
*/
writel(0, &pGbl->rxq_start_addr.value);
- writel(etdev->RegistryRxMemEnd,
+ writel(PARM_RX_MEM_END_DEF,
&pGbl->rxq_end_addr.value);
- writel(etdev->RegistryRxMemEnd + 1,
+ writel(PARM_RX_MEM_END_DEF + 1,
&pGbl->txq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1,
&pGbl->txq_end_addr.value);
* For version B silicon, this value gets updated once autoneg is
*complete.
*/
- writel(etdev->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
+ writel(PARM_RX_NUM_BUFS_DEF, &pRxDma->num_pkt_done.value);
/* The "time_done" is not working correctly to coalesce interrupts
* after a given time period, but rather is giving us an interrupt
* regardless of whether we have received packets.
* This value gets updated once autoneg is complete.
*/
- writel(etdev->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
+ writel(PARM_RX_TIME_INT_DEF, &pRxDma->max_pkt_time.value);
spin_unlock_irqrestore(&etdev->RcvLock, flags);
if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
etdev->RxRing.UnfinishedReceives = true;
- writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+ writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
&etdev->regs->global.watchdog_timer);
} else {
/* Watchdog timer will disable itself if appropriate. */
#include "et1310_tx.h"
+
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
if (++etdev->TxRing.TxPacketsSinceLastinterrupt ==
- etdev->RegistryTxNumBuffers) {
+ PARM_TX_NUM_BUFS_DEF) {
CurDesc[FragmentNumber - 1].word3.value = 0x5;
etdev->TxRing.TxPacketsSinceLastinterrupt = 0;
} else {
* timer to wake us up if this packet isn't followed by N more.
*/
if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
- writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+ writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
&etdev->regs->global.watchdog_timer);
}
TRUEPHY_SPEED_1000MBPS) {
if (++etdev->TxRing.
TxPacketsSinceLastinterrupt >=
- etdev->RegistryTxNumBuffers) {
+ PARM_TX_NUM_BUFS_DEF) {
CurDesc.word3.value = 0x5;
etdev->TxRing.
TxPacketsSinceLastinterrupt
if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
if (++etdev->TxRing.TxPacketsSinceLastinterrupt >=
- etdev->RegistryTxNumBuffers) {
+ PARM_TX_NUM_BUFS_DEF) {
CurDesc.word3.value = 0x5;
etdev->TxRing.TxPacketsSinceLastinterrupt =
0;
* timer to wake us up if this packet isn't followed by N more.
*/
if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
- writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+ writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
&etdev->regs->global.watchdog_timer);
}
u32 RegistryVlanTag; /* 802.1q Vlan TAG */
u32 RegistryJumboPacket; /* Max supported ethernet packet size */
- u32 RegistryTxNumBuffers;
- u32 RegistryTxTimeInterval;
-
- u32 RegistryRxNumBuffers;
- u32 RegistryRxTimeInterval;
-
/* Validation helpers */
u8 RegistryNMIDisable;
u8 RegistryPhyLoopbk; /* Enable Phy loopback */
#define PARM_PHY_COMA_MIN 0
#define PARM_PHY_COMA_MAX 1
-#define PARM_RX_NUM_BUFS_DEF 4
-#define PARM_RX_NUM_BUFS_MIN 1
-#define PARM_RX_NUM_BUFS_MAX 64
-
-#define PARM_RX_TIME_INT_DEF 10
-#define PARM_RX_TIME_INT_MIN 2
-#define PARM_RX_TIME_INT_MAX 320
-
-#define PARM_TX_NUM_BUFS_DEF 4
-#define PARM_TX_NUM_BUFS_MIN 1
-#define PARM_TX_NUM_BUFS_MAX 40
-
-#define PARM_TX_TIME_INT_DEF 40
-#define PARM_TX_TIME_INT_MIN 1
-#define PARM_TX_TIME_INT_MAX 140
-
-#define PARM_RX_MEM_END_DEF 0x2bc
-#define PARM_RX_MEM_END_MIN 0
-#define PARM_RX_MEM_END_MAX 0x3ff
-
#define PARM_MAC_STAT_DEF 1
#define PARM_MAC_STAT_MIN 0
#define PARM_MAC_STAT_MAX 1
#define PARM_NMI_DISABLE_MAX 2
#define PARM_DMA_CACHE_DEF 0
-#define PARM_DMA_CACHE_MIN 0
-#define PARM_DMA_CACHE_MAX 15
#define PARM_PHY_LOOPBK_DEF 0
#define PARM_PHY_LOOPBK_MIN 0
etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
- etdev->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;
- etdev->RegistryRxTimeInterval = PARM_RX_TIME_INT_DEF;
- etdev->RegistryTxNumBuffers = PARM_TX_NUM_BUFS_DEF;
- etdev->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
- etdev->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
etdev->RegistryMACStat = PARM_MAC_STAT_DEF;
if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
/* Define order of magnitude converter */
#define NANO_IN_A_MICRO 1000
+#define PARM_RX_NUM_BUFS_DEF 4
+#define PARM_RX_TIME_INT_DEF 10
+#define PARM_RX_MEM_END_DEF 0x2bc
+#define PARM_TX_TIME_INT_DEF 40
+#define PARM_TX_NUM_BUFS_DEF 4
+#define PARM_DMA_CACHE_DEF 0
+
+
#endif /* __ET131X_DEFS_H__ */