radeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK
authorMarek Olšák <marek.olsak@amd.com>
Thu, 17 Jan 2019 19:49:02 +0000 (14:49 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 22 Jan 2019 17:14:26 +0000 (12:14 -0500)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_state_draw.c

index 6ed45bb..b6953b8 100644 (file)
@@ -528,7 +528,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
                /* Initialize the memory. */
                struct radeon_cmdbuf *cs = sctx->gfx_cs;
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
+               radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
+                                                                     : V_370_MEM_GRBM) |
                            S_370_WR_CONFIRM(1) |
                            S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
index ea8c5d0..9a80bd8 100644 (file)
@@ -1596,7 +1596,8 @@ void si_trace_emit(struct si_context *sctx)
        uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
+       radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
+                                                             : V_370_MEM_GRBM) |
                    S_370_WR_CONFIRM(1) |
                    S_370_ENGINE_SEL(V_370_ME));
        radeon_emit(cs, va);