ts->irq_disabled = 0;
enable_irq(spi->irq);
- if (req->msg.status)
- status = req->msg.status;
-
- /* on-wire is a must-ignore bit, a BE12 value, then padding */
- sample = be16_to_cpu(req->sample);
- sample = sample >> 3;
- sample &= 0x0fff;
+ if (status == 0) {
+ /* on-wire is a must-ignore bit, a BE12 value, then padding */
+ sample = be16_to_cpu(req->sample);
+ sample = sample >> 3;
+ sample &= 0x0fff;
+ }
kfree(req);
return status ? status : sample;
DMA_FROM_DEVICE);
status = spi_sync(host->spi, &host->readback);
- if (status == 0)
- status = host->readback.status;
if (host->dma_dev)
dma_sync_single_for_cpu(host->dma_dev,
DMA_BIDIRECTIONAL);
}
status = spi_sync(host->spi, &host->m);
- if (status == 0)
- status = host->m.status;
if (host->dma_dev)
dma_sync_single_for_cpu(host->dma_dev,
DMA_BIDIRECTIONAL);
status = spi_sync(spi, &host->m);
- if (status == 0)
- status = host->m.status;
if (status != 0) {
dev_dbg(&spi->dev, "write error (%d)\n", status);
}
status = spi_sync(spi, &host->m);
- if (status == 0)
- status = host->m.status;
if (host->dma_dev) {
dma_sync_single_for_cpu(host->dma_dev,
DMA_BIDIRECTIONAL);
tmp = spi_sync(spi, &host->m);
- if (tmp == 0)
- tmp = host->m.status;
if (host->dma_dev)
dma_sync_single_for_cpu(host->dma_dev,
/* do the i/o */
status = spi_sync(spi, &message);
- if (status == 0)
- status = message.status;
- else
- return status;
-
- *data = chip->rx_buf[1];
+ if (status == 0)
+ *data = chip->rx_buf[1];
return status;
}
/* do the i/o */
status = spi_sync(spi, &message);
- if (status == 0)
- status = message.status;
- else
+ if (status)
return status;
/* The chip sends data in this order: