Merge patch series "Add non-coherent DMA support for AX45MP"

Prabhakar <prabhakar.csengg@gmail.com> says:

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

non-coherent DMA support for AX45MP
====================================

On the Andes AX45MP core, cache coherency is a specification option so it
may not be supported. In this case DMA will fail. To get around with this
issue this patch series does the below:

1] Andes alternative ports is implemented as errata which checks if the
IOCP is missing and only then applies to CMO errata. One vendor specific
SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of
errata.

Below are the configs which Andes port provides (and are selected by
RZ/Five):
      - ERRATA_ANDES
      - ERRATA_ANDES_CMO

OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now
part v1.3 release.

2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
OpenSBI configures the PMA regions as required and creates a reserve memory
node and propagates it to the higher boot stack.

Currently OpenSBI (upstream) configures the required PMA region and passes
this a shared DMA pool to Linux.

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        pma_resv0@58000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x58000000 0x0 0x08000000>;
            no-map;
            linux,dma-default;
        };
    };

The above shared DMA pool gets appended to Linux DTB so the DMA memory
requests go through this region.

3] We provide callbacks to synchronize specific content between memory and
cache.

4] RZ/Five SoC selects the below configs
        - AX45MP_L2_CACHE
        - DMA_GLOBAL_POOL
        - ERRATA_ANDES
        - ERRATA_ANDES_CMO

----------x---------------------x--------------------x---------------x----

* b4-shazam-merge:
  soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
  cache: Add L2 cache management for Andes AX45MP RISC-V core
  dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
  riscv: mm: dma-noncoherent: nonstandard cache operations support
  riscv: errata: Add Andes alternative ports
  riscv: asm: vendorid_list: Add Andes Technology to the vendors list

Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc MAINTAINERS
Simple merge

diff --cc arch/riscv/Kconfig
index 5138dce,3c20879..4680637
--- 1/arch/riscv/Kconfig
--- 2/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@@ -272,9 -267,15 +272,16 @@@ config RISCV_DMA_NONCOHEREN
        select ARCH_HAS_SETUP_DMA_OPS
        select ARCH_HAS_SYNC_DMA_FOR_CPU
        select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 +      select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
        select DMA_DIRECT_REMAP
  
+ config RISCV_NONSTANDARD_CACHE_OPS
+       bool
+       depends on RISCV_DMA_NONCOHERENT
+       help
+         This enables function pointer support for non-standard noncoherent
+         systems to handle cache management.
+ 
  config AS_HAS_INSN
        def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
  

diff --cc arch/riscv/include/asm/alternative.h
Simple merge

diff --cc arch/riscv/kernel/alternative.c
index 8505615,b034599..319a1da
--- 1/arch/riscv/kernel/alternative.c
--- 2/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@@ -41,7 -43,13 +41,12 @@@ static void riscv_fill_cpu_mfr_info(str
        cpu_mfr_info->imp_id = sbi_get_mimpid();
  #endif
  
 -      cpu_mfr_info->feature_probe_func = NULL;
        switch (cpu_mfr_info->vendor_id) {
+ #ifdef CONFIG_ERRATA_ANDES
+       case ANDESTECH_VENDOR_ID:
+               cpu_mfr_info->patch_func = andes_errata_patch_func;
+               break;
+ #endif
  #ifdef CONFIG_ERRATA_SIFIVE
        case SIFIVE_VENDOR_ID:
                cpu_mfr_info->patch_func = sifive_errata_patch_func;

diff --cc arch/riscv/mm/dma-noncoherent.c
index f269990,a4f3f37..b76e7e1
--- 1/arch/riscv/mm/dma-noncoherent.c
--- 2/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@@ -9,11 -9,16 +9,18 @@@
  #include <linux/dma-map-ops.h>
  #include <linux/mm.h>
  #include <asm/cacheflush.h>
+ #include <asm/dma-noncoherent.h>
  
  static bool noncoherent_supported __ro_after_init;
 +int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
 +EXPORT_SYMBOL_GPL(dma_cache_alignment);
  
+ struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init = {
+       .wback = NULL,
+       .inv = NULL,
+       .wback_inv = NULL,
+ };
+ 
  static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
  {
        void *vaddr = phys_to_virt(paddr);
@@@ -123,8 -155,11 +157,17 @@@ void riscv_noncoherent_supported(void
        noncoherent_supported = true;
  }
  
 +void __init riscv_set_dma_cache_alignment(void)
 +{
 +      if (!noncoherent_supported)
 +              dma_cache_alignment = 1;
 +}
++
+ void riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops)
+ {
+       if (!ops)
+               return;
+ 
+       noncoherent_cache_ops = *ops;
+ }
+ EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);

diff --cc drivers/Kconfig
Simple merge

diff --cc drivers/Makefile
Simple merge