*/
if (intel_device_info_is_atsm(device->info) &&
queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) {
- anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
- pc.CommandStreamerStallEnable = true;
- pc.StateCacheInvalidationEnable = true;
- pc.ConstantCacheInvalidationEnable = true;
- pc.UntypedDataPortCacheFlushEnable = true;
- pc.TextureCacheInvalidationEnable = true;
- pc.InstructionCacheInvalidateEnable = true;
- pc.HDCPipelineFlushEnable = true;
+ genX(batch_emit_pipe_control)
+ (batch, device->info,
+ ANV_PIPE_CS_STALL_BIT |
+ ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
+ ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
+ ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT |
+ ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
+ ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
+ ANV_PIPE_HDC_PIPELINE_FLUSH_BIT);
}
}
#endif
#if GFX_VER >= 12
#if GFX_VERx10 >= 125
- anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
- /* Wa_14016407139:
- *
- * "On Surface state base address modification, for 3D workloads, SW must
- * always program PIPE_CONTROL either with CS Stall or PS sync stall. In
- * both the cases set Render Target Cache Flush Enable".
- */
- pc.RenderTargetCacheFlushEnable = true;
- pc.CommandStreamerStallEnable = true;
- }
+ /* Wa_14016407139:
+ *
+ * "On Surface state base address modification, for 3D workloads, SW must
+ * always program PIPE_CONTROL either with CS Stall or PS sync stall. In
+ * both the cases set Render Target Cache Flush Enable".
+ */
+ genX(batch_emit_pipe_control)
+ (batch, device->info, ANV_PIPE_CS_STALL_BIT |
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT);
#endif
/* GEN:BUG:1607854226:
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_TASK), zero);
/* Issue 'nullprim' to commit the state. */
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.PostSyncOperation = WriteImmediateData;
- pc.Address = cmd_buffer->device->workaround_address;
- }
+ genX(batch_emit_pipe_control_write)
+ (&cmd_buffer->batch, cmd_buffer->device->info,
+ WriteImmediateData, cmd_buffer->device->workaround_address, 0, 0);
#endif
}