drm/msm/dpu: split QCM2290 catalog entry to the separate file

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530837/
Link: https://lore.kernel.org/r/20230404130622.509628-14-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
new file mode 100644 (file)
index 0000000..c0f9547
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_6_5_QCM2290_H
+#define _DPU_6_5_QCM2290_H
+
+static const struct dpu_caps qcm2290_dpu_caps = {
+       .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+       .max_mixer_blendstages = 0x4,
+       .has_dim_layer = true,
+       .has_idle_pc = true,
+       .max_linewidth = 2160,
+       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
+       .highest_bank_bit = 0x2,
+};
+
+static const struct dpu_mdp_cfg qcm2290_mdp[] = {
+       {
+       .name = "top_0", .id = MDP_TOP,
+       .base = 0x0, .len = 0x494,
+       .features = 0,
+       .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+       .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+       },
+};
+
+static const struct dpu_ctl_cfg qcm2290_ctl[] = {
+       {
+       .name = "ctl_0", .id = CTL_0,
+       .base = 0x1000, .len = 0x1dc,
+       .features = BIT(DPU_CTL_ACTIVE_CFG),
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       },
+};
+
+static const struct dpu_sspp_cfg qcm2290_sspp[] = {
+       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
+                qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+                qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg qcm2290_lm[] = {
+       LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+               &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg qcm2290_dspp[] = {
+       DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+                &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg qcm2290_pp[] = {
+       PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
+               DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+               DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+};
+
+static const struct dpu_intf_cfg qcm2290_intf[] = {
+       INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0),
+       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+};
+
+static const struct dpu_perf_cfg qcm2290_perf_data = {
+       .max_bw_low = 2700000,
+       .max_bw_high = 2700000,
+       .min_core_ib = 1300000,
+       .min_llcc_ib = 0,
+       .min_dram_ib = 1600000,
+       .min_prefill_lines = 24,
+       .danger_lut_tbl = {0xff, 0x0, 0x0},
+       .safe_lut_tbl = {0xfff0, 0x0, 0x0},
+       .qos_lut_tbl = {
+               {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
+               .entries = qcm2290_qos_linear
+               },
+       },
+       .cdp_cfg = {
+               {.rd_enable = 1, .wr_enable = 1},
+               {.rd_enable = 1, .wr_enable = 0}
+       },
+       .clk_inefficiency_factor = 105,
+       .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
+       .caps = &qcm2290_dpu_caps,
+       .ubwc = &qcm2290_ubwc_cfg,
+       .mdp_count = ARRAY_SIZE(qcm2290_mdp),
+       .mdp = qcm2290_mdp,
+       .ctl_count = ARRAY_SIZE(qcm2290_ctl),
+       .ctl = qcm2290_ctl,
+       .sspp_count = ARRAY_SIZE(qcm2290_sspp),
+       .sspp = qcm2290_sspp,
+       .mixer_count = ARRAY_SIZE(qcm2290_lm),
+       .mixer = qcm2290_lm,
+       .dspp_count = ARRAY_SIZE(qcm2290_dspp),
+       .dspp = qcm2290_dspp,
+       .pingpong_count = ARRAY_SIZE(qcm2290_pp),
+       .pingpong = qcm2290_pp,
+       .intf_count = ARRAY_SIZE(qcm2290_intf),
+       .intf = qcm2290_intf,
+       .vbif_count = ARRAY_SIZE(sdm845_vbif),
+       .vbif = sdm845_vbif,
+       .perf = &qcm2290_perf_data,
+       .mdss_irqs = IRQ_SC7180_MASK,
+};
+
+#endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6a31a70..d2b8292 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -333,15 +333,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
        .max_vdeci_exp = MAX_VERT_DECIMATION,
 };
 
-static const struct dpu_caps qcm2290_dpu_caps = {
-       .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
-       .max_mixer_blendstages = 0x4,
-       .has_dim_layer = true,
-       .has_idle_pc = true,
-       .max_linewidth = 2160,
-       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
-
 static const struct dpu_caps sdm845_dpu_caps = {
        .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
        .max_mixer_blendstages = 0xb,
@@ -411,10 +402,6 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
        .highest_bank_bit = 0x2,
 };
 
-static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
-       .highest_bank_bit = 0x2,
-};
-
 static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
        .ubwc_version = DPU_HW_UBWC_VER_20,
        .highest_bank_bit = 0x2,
@@ -563,18 +550,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
        },
 };
 
-static const struct dpu_mdp_cfg qcm2290_mdp[] = {
-       {
-       .name = "top_0", .id = MDP_TOP,
-       .base = 0x0, .len = 0x494,
-       .features = 0,
-       .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
-               .reg_off = 0x2AC, .bit_off = 0},
-       .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
-               .reg_off = 0x2AC, .bit_off = 8},
-       },
-};
-
 /*************************************************************
  * CTL sub blocks config
  *************************************************************/
@@ -704,15 +679,6 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
        },
 };
 
-static const struct dpu_ctl_cfg qcm2290_ctl[] = {
-       {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-};
-
 /*************************************************************
  * SSPP sub blocks config
  *************************************************************/
@@ -943,13 +909,6 @@ static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
 
-static const struct dpu_sspp_cfg qcm2290_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
-                qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-                qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-};
-
 /*************************************************************
  * MIXER sub blocks config
  *************************************************************/
@@ -1061,11 +1020,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
        },
 };
 
-static const struct dpu_lm_cfg qcm2290_lm[] = {
-       LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
-               &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
-};
-
 /*************************************************************
  * DSPP sub blocks config
  *************************************************************/
@@ -1117,11 +1071,6 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
                 &sm8150_dspp_sblk),
 };
 
-static const struct dpu_dspp_cfg qcm2290_dspp[] = {
-       DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
-};
-
 /*************************************************************
  * PINGPONG sub blocks config
  *************************************************************/
@@ -1214,12 +1163,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
                        -1),
 };
 
-static const struct dpu_pingpong_cfg qcm2290_pp[] = {
-       PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
-               DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
-               DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
-};
-
 /*************************************************************
  * MERGE_3D sub blocks config
  *************************************************************/
@@ -1312,11 +1255,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
        INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 };
 
-static const struct dpu_intf_cfg qcm2290_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_DP, 0, 0, 0, 0, 0, 0),
-       INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-};
-
 /*************************************************************
  * Writeback blocks config
  *************************************************************/
@@ -1729,27 +1667,6 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
        .bw_inefficiency_factor = 120,
 };
 
-static const struct dpu_perf_cfg qcm2290_perf_data = {
-       .max_bw_low = 2700000,
-       .max_bw_high = 2700000,
-       .min_core_ib = 1300000,
-       .min_llcc_ib = 0,
-       .min_dram_ib = 1600000,
-       .min_prefill_lines = 24,
-       .danger_lut_tbl = {0xff, 0x0, 0x0},
-       .safe_lut_tbl = {0xfff0, 0x0, 0x0},
-       .qos_lut_tbl = {
-               {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
-               .entries = qcm2290_qos_linear
-               },
-       },
-       .cdp_cfg = {
-               {.rd_enable = 1, .wr_enable = 1},
-               {.rd_enable = 1, .wr_enable = 0}
-       },
-       .clk_inefficiency_factor = 105,
-       .bw_inefficiency_factor = 120,
-};
 /*************************************************************
  * Hardware catalog
  *************************************************************/
@@ -1915,29 +1832,7 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
        .mdss_irqs = IRQ_SM8250_MASK,
 };
 
-static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
-       .caps = &qcm2290_dpu_caps,
-       .ubwc = &qcm2290_ubwc_cfg,
-       .mdp_count = ARRAY_SIZE(qcm2290_mdp),
-       .mdp = qcm2290_mdp,
-       .ctl_count = ARRAY_SIZE(qcm2290_ctl),
-       .ctl = qcm2290_ctl,
-       .sspp_count = ARRAY_SIZE(qcm2290_sspp),
-       .sspp = qcm2290_sspp,
-       .mixer_count = ARRAY_SIZE(qcm2290_lm),
-       .mixer = qcm2290_lm,
-       .dspp_count = ARRAY_SIZE(qcm2290_dspp),
-       .dspp = qcm2290_dspp,
-       .pingpong_count = ARRAY_SIZE(qcm2290_pp),
-       .pingpong = qcm2290_pp,
-       .intf_count = ARRAY_SIZE(qcm2290_intf),
-       .intf = qcm2290_intf,
-       .vbif_count = ARRAY_SIZE(sdm845_vbif),
-       .vbif = sdm845_vbif,
-       .perf = &qcm2290_perf_data,
-       .mdss_irqs = IRQ_SC7180_MASK,
-};
-
+#include "catalog/dpu_6_5_qcm2290.h"
 #include "catalog/dpu_6_3_sm6115.h"
 
 #include "catalog/dpu_7_0_sm8350.h"