drm/i915/tgl: Add memory type decoding for bandwidth checking

The memory type values have changed in TGL, so we need to translate them
differently than ICL. While we're moving it, fix up the ICL translation
for LPDDR4.

BSpec: 53998

v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190924222829.13142-1-james.ausmus@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index cd58e47..22e83f8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -35,22 +35,45 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
        if (ret)
                return ret;
 
-       switch (val & 0xf) {
-       case 0:
-               qi->dram_type = INTEL_DRAM_DDR4;
-               break;
-       case 1:
-               qi->dram_type = INTEL_DRAM_DDR3;
-               break;
-       case 2:
-               qi->dram_type = INTEL_DRAM_LPDDR3;
-               break;
-       case 3:
-               qi->dram_type = INTEL_DRAM_LPDDR3;
-               break;
-       default:
-               MISSING_CASE(val & 0xf);
-               break;
+       if (IS_GEN(dev_priv, 12)) {
+               switch (val & 0xf) {
+               case 0:
+                       qi->dram_type = INTEL_DRAM_DDR4;
+                       break;
+               case 3:
+                       qi->dram_type = INTEL_DRAM_LPDDR4;
+                       break;
+               case 4:
+                       qi->dram_type = INTEL_DRAM_DDR3;
+                       break;
+               case 5:
+                       qi->dram_type = INTEL_DRAM_LPDDR3;
+                       break;
+               default:
+                       MISSING_CASE(val & 0xf);
+                       break;
+               }
+       } else if (IS_GEN(dev_priv, 11)) {
+               switch (val & 0xf) {
+               case 0:
+                       qi->dram_type = INTEL_DRAM_DDR4;
+                       break;
+               case 1:
+                       qi->dram_type = INTEL_DRAM_DDR3;
+                       break;
+               case 2:
+                       qi->dram_type = INTEL_DRAM_LPDDR3;
+                       break;
+               case 3:
+                       qi->dram_type = INTEL_DRAM_LPDDR4;
+                       break;
+               default:
+                       MISSING_CASE(val & 0xf);
+                       break;
+               }
+       } else {
+               MISSING_CASE(INTEL_GEN(dev_priv));
+               qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
        }
 
        qi->num_channels = (val & 0xf0) >> 4;