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clk: zynqmp: Extend driver for versal
author
Rajan Vaja
<rajan.vaja@xilinx.com>
Thu, 5 Dec 2019 06:35:55 +0000
(22:35 -0800)
committer
Stephen Boyd
<sboyd@kernel.org>
Thu, 23 Jan 2020 21:22:44 +0000
(13:22 -0800)
Add Versal compatible string to support Versal
binding.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link:
https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/zynqmp/clkc.c
patch
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diff --git
a/drivers/clk/zynqmp/clkc.c
b/drivers/clk/zynqmp/clkc.c
index
a11f93e
..
10e89f2
100644
(file)
--- a/
drivers/clk/zynqmp/clkc.c
+++ b/
drivers/clk/zynqmp/clkc.c
@@
-2,7
+2,7
@@
/*
* Zynq UltraScale+ MPSoC clock controller
*
- * Copyright (C) 2016-201
8
Xilinx
+ * Copyright (C) 2016-201
9
Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@@
-749,6
+749,7
@@
static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
+ {.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);