PCI: xilinx-nwl: Fix coding style violations
authorMichal Simek <michal.simek@amd.com>
Thu, 8 Dec 2022 12:38:50 +0000 (13:38 +0100)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 8 Dec 2022 16:50:48 +0000 (10:50 -0600)
Fix code alignments and remove additional newline.

Link: https://lore.kernel.org/r/17c75e7003bb8c43a0f45ae3d7c45cac230ef852.1670503129.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/controller/pcie-xilinx-nwl.c

index 40d070e..e10a586 100644 (file)
@@ -474,15 +474,15 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 
        for (i = 0; i < nr_irqs; i++) {
                irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
-                               domain->host_data, handle_simple_irq,
-                               NULL, NULL);
+                                   domain->host_data, handle_simple_irq,
+                                   NULL, NULL);
        }
        mutex_unlock(&msi->lock);
        return 0;
 }
 
 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
-                                       unsigned int nr_irqs)
+                               unsigned int nr_irqs)
 {
        struct irq_data *data = irq_domain_get_irq_data(domain, virq);
        struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -722,7 +722,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
        /* Enable all misc interrupts */
        nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
 
-
        /* Disable all legacy interrupts */
        nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);