}
}
- radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
+ if (db_count_control != cmd_buffer->state.last_db_count_control) {
+ radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
- cmd_buffer->state.context_roll_without_scissor_emitted = true;
+ cmd_buffer->state.context_roll_without_scissor_emitted = true;
+
+ cmd_buffer->state.last_db_count_control = db_count_control;
+ }
}
unsigned
cmd_buffer->state.last_vrs_rates = -1;
cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;
cmd_buffer->state.last_pa_sc_binner_cntl_0 = -1;
+ cmd_buffer->state.last_db_count_control = -1;
cmd_buffer->usage_flags = pBeginInfo->flags;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL | RADV_CMD_DIRTY_GUARDBAND |
primary->state.last_first_instance = -1;
primary->state.last_drawid = -1;
primary->state.last_vertex_offset = -1;
+ primary->state.last_db_count_control = -1;
}
static void
uint32_t last_sx_blend_opt_epsilon;
uint32_t last_sx_blend_opt_control;
+ uint32_t last_db_count_control;
+
/* Whether CP DMA is busy/idle. */
bool dma_is_busy;