def Vector_MaskedLoadOp :
Vector_Op<"maskedload">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemRead]>:$base,
Variadic<Index>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
def Vector_MaskedStoreOp :
Vector_Op<"maskedstore">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemWrite]>:$base,
Variadic<Index>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {
def Vector_GatherOp :
Vector_Op<"gather">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemRead]>:$base,
VectorOfRankAndType<[1], [AnyInteger]>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
def Vector_ScatterOp :
Vector_Op<"scatter">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemWrite]>:$base,
VectorOfRankAndType<[1], [AnyInteger]>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {
def Vector_ExpandLoadOp :
Vector_Op<"expandload">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemRead]>:$base,
Variadic<Index>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
def Vector_CompressStoreOp :
Vector_Op<"compressstore">,
- Arguments<(ins AnyMemRef:$base,
+ Arguments<(ins Arg<AnyMemRef, "", [MemWrite]>:$base,
Variadic<Index>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {
vector<1x4xf32>, tensor<4x4xf32>
return
}
+
+// -----
+
+// CHECK-LABEL: func @dead_load
+// CHECK-NOT: vector.maskedload
+// CHECK-NOT: vector.gather
+// CHECK-NOT: vector.expandload
+// CHECK: return
+func @dead_load(%base: memref<?xf32>, %indices: vector<16xi32>,
+ %mask: vector<16xi1>, %passthru: vector<16xf32>) {
+ %c0 = constant 0 : index
+ %0 = vector.maskedload %base[%c0], %mask, %passthru :
+ memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+ %1 = vector.gather %base[%indices], %mask, %passthru :
+ memref<?xf32>, vector<16xi32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+ %2 = vector.expandload %base[%c0], %mask, %passthru :
+ memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+ return
+}