struct brw_reg src[4], dst;
unsigned int last_insn_offset = p->next_insn_offset;
bool multiple_instructions_emitted = false;
+ tgl_swsb swsb = inst->sched;
/* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
* "Register Region Restrictions" section: for BDW, SKL:
brw_set_default_exec_size(p, BRW_EXECUTE_16);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
+ brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
last_insn_offset = p->next_insn_offset;
+ swsb = tgl_swsb_dst_dep(swsb, 1);
}
if (!is_accum_used && !inst->eot) {
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);
- brw_set_default_swsb(p, inst->sched);
+ brw_set_default_swsb(p, swsb);
unsigned exec_size = inst->exec_size;
if (devinfo->verx10 == 70 &&
}
case FS_OPCODE_SCHEDULING_FENCE:
- if (inst->sources == 0 && inst->sched.regdist == 0 &&
- inst->sched.mode == TGL_SBID_NULL) {
+ if (inst->sources == 0 && swsb.regdist == 0 &&
+ swsb.mode == TGL_SBID_NULL) {
if (unlikely(debug_flag))
disasm_info->use_tail = true;
break;