configs: ls1088ardb: enable CONFIG_DM_ETH and related
authorIoana Ciornei <ioana.ciornei@nxp.com>
Wed, 18 Mar 2020 14:47:47 +0000 (16:47 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Wed, 29 Apr 2020 05:40:54 +0000 (11:10 +0530)
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS1088ARDB board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
configs/ls1088ardb_tfa_defconfig
include/configs/ls1088ardb.h

index 89e9a46..d2fca24 100644 (file)
@@ -21,6 +21,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -40,8 +41,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index 3c2fda4..1c3d9e4 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -43,8 +44,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index da41cca..cb74b2d 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -52,8 +53,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index 0483e5d..9497e3d 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -53,8 +54,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index 079e6c5..e64c976 100644 (file)
@@ -24,6 +24,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -47,8 +48,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index e3d4b02..94fe6db 100644 (file)
@@ -25,6 +25,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -52,8 +53,12 @@ CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_FSL_LS_MDIO=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
index b48efcc..1464827 100644 (file)
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
+#ifndef CONFIG_TARGET_LS1088ARDB
 #define CONFIG_PHYLIB
+#endif
 
 #define CONFIG_PHY_VITESSE
 #define AQ_PHY_ADDR1                   0x00