drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order

Starting with TGL the disabling order of HDMI transcoder clock vs. DDI
BUF has swapped, fix this. There hasn't been any issues seen related to
this, but let's follow the spec.

Reported-by: Sandeep K Lakkakula <sandeep.k.lakkakula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f76eb6e345ec92eff7b7360d9c51a19a12d43e71..ec131973f37429a6f21717437bea8cf200580949 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
        dig_port->set_infoframes(encoder, false,
                                 old_crtc_state, old_conn_state);
 
-       intel_ddi_disable_pipe_clock(old_crtc_state);
+       if (DISPLAY_VER(dev_priv) < 12)
+               intel_ddi_disable_pipe_clock(old_crtc_state);
 
        intel_disable_ddi_buf(encoder, old_crtc_state);
 
+       if (DISPLAY_VER(dev_priv) >= 12)
+               intel_ddi_disable_pipe_clock(old_crtc_state);
+
        intel_display_power_put(dev_priv,
                                dig_port->ddi_io_power_domain,
                                fetch_and_zero(&dig_port->ddi_io_wakeref));