crt_reg.ver_sync_end += crt_reg.ver_sync_start;
h_addr = crt_reg.hor_addr;
v_addr = crt_reg.ver_addr;
- if (set_iga == IGA1) {
- viafb_unlock_crt();
- viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
- }
-
if (set_iga == IGA1)
via_set_primary_timing(&crt_reg);
else if (set_iga == IGA2)
via_set_secondary_timing(&crt_reg);
- viafb_lock_crt();
- viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
/* load FIFO */
/* lock timing registers */
via_write_reg_mask(VIACR, 0x11, 0x80, 0x80);
+
+ /* reset timing control */
+ via_write_reg_mask(VIACR, 0x17, 0x00, 0x80);
+ via_write_reg_mask(VIACR, 0x17, 0x80, 0x80);
}
void via_set_secondary_timing(const struct display_timing *timing)