MIPS: csrc-r4k: Refine rating computation

Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level mips_hpt_frequency.

Cap rating of csrc-r4k into 299 to ensure it doesn't go into
"Desired" range, given all the drama we have with CP0 count
registers (SMP sync, behaviour on wait etc).

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index edc4afc080faaa1dfa589ff9b7c6610270d68627..f02ae333f4f958e697aec059564529f93d9d35f0 100644 (file)
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void)
                return -ENXIO;
 
        /* Calculate a somewhat reasonable rating value */
-       clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+       clocksource_mips.rating = 200;
+       clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);
 
        /*
         * R2 onwards makes the count accessible to user mode so it can be used