arm64: dts: msm8916: fix gic_irq_domain_translate warnings
authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Wed, 18 Apr 2018 16:34:15 +0000 (17:34 +0100)
committerAndy Gross <andy.gross@linaro.org>
Wed, 23 May 2018 04:28:54 +0000 (23:28 -0500)
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b56b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Thierry Escande <thierry.escande@linaro.org>
Tested-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
arch/arm64/boot/dts/qcom/msm8916.dtsi

index 66b318e..650f356 100644 (file)
 
        pmu {
                compatible = "arm,cortex-a53-pmu";
-               interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
        };
 
        thermal-zones {
                blsp_i2c2: i2c@78b6000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x078b6000 0x500>;
-                       interrupts = <GIC_SPI 96 0>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
                        clock-names = "iface", "core";
                blsp_i2c4: i2c@78b8000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x078b8000 0x500>;
-                       interrupts = <GIC_SPI 98 0>;
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
                        clock-names = "iface", "core";
                blsp_i2c6: i2c@78ba000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x078ba000 0x500>;
-                       interrupts = <GIC_SPI 100 0>;
+                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
                        clock-names = "iface", "core";
                                        "mi2s-bit-clk3";
                        #sound-dai-cells = <1>;
 
-                       interrupts = <0 160 0>;
+                       interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "lpass-irq-lpaif";
                        reg = <0x07708000 0x10000>;
                        reg-names = "lpass-lpaif";
                        reg = <0x07824900 0x11c>, <0x07824000 0x800>;
                        reg-names = "hc_mem", "core_mem";
 
-                       interrupts = <0 123 0>, <0 138 0>;
+                       interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
                        clocks = <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&gcc GCC_SDCC1_AHB_CLK>,
                        reg = <0x07864900 0x11c>, <0x07864000 0x800>;
                        reg-names = "hc_mem", "core_mem";
 
-                       interrupts = <0 125 0>, <0 221 0>;
+                       interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
                        clocks = <&gcc GCC_SDCC2_APPS_CLK>,
                                 <&gcc GCC_SDCC2_AHB_CLK>,
                        iommu-ctx@2000 {
                                compatible = "qcom,msm-iommu-v1-ns";
                                reg = <0x2000 0x1000>;
-                               interrupts = <GIC_SPI 242 0>;
+                               interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
                                      "bus_clk",
                                      "vsync_clk";
 
-                       interrupts = <0 72 0>;
+                       interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 
                        interrupt-controller;
                        #interrupt-cells = <1>;