s->id = env->cpuid_apic_id;
s->cpu_env = env;
- apic_reset(s);
msix_supported = 1;
/* XXX: mapping more APICs at the same memory location */
qemu_format_nic_info_str(d->vc, macaddr);
vmstate_register(-1, &vmstate_e1000, d);
- e1000_reset(d);
if (!pci_dev->qdev.hotplugged) {
static int loaded = 0;
HPETTimer *timer = &s->timer[i];
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
}
- hpet_reset(s);
vmstate_register(-1, &vmstate_hpet, s);
qemu_register_reset(hpet_reset, s);
/* HPET Area */
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);
- pit_reset(pit);
-
return pit;
}
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
qemu_register_reset(piix3_reset, d);
- piix3_reset(d);
pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
piix4_dev = d;
- piix4_reset(d);
qemu_register_reset(piix4_reset, d);
return 0;
}
pci_conf[PCI_HEADER_TYPE] =
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
- piix3_reset(d);
qemu_register_reset(piix3_reset, d);
return 0;
}
PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
- rtl8139_reset(&s->dev.qdev);
+
s->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC,
s->conf.vlan, s->conf.peer,
dev->qdev.info->name, dev->qdev.id,
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
qemu_register_reset(serial_reset, s);
- serial_reset(s);
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
serial_event, s);
ohci->async_td = 0;
qemu_register_reset(ohci_reset, ohci);
- ohci_reset(ohci);
}
typedef struct {
s->num_ports_vmstate = NB_PORTS;
qemu_register_reset(uhci_reset, s);
- uhci_reset(s);
/* Use region 4 for consistency with real hardware. BSD guests seem
to rely on this. */
s->update_retrace_info = vga_precise_update_retrace_info;
break;
}
- vga_reset(s);
}
/* used by both ISA and PCI */
return NULL;
}
mce_init(env);
+#ifdef CONFIG_USER_ONLY
cpu_reset(env);
+#endif
qemu_init_vcpu(env);
qemu_system_ready = 1;
qemu_cond_broadcast(&qemu_system_cond);
#endif
+ qemu_system_reset();
for (;;) {
do {