// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.c originally written by
#include <common.h>
#include <bootstage.h>
#include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
-#include "dockstar.h"
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
+#define DOCKSTAR_OE_LOW (~(0))
+#define DOCKSTAR_OE_HIGH (~(0))
+#define DOCKSTAR_OE_VAL_LOW BIT(29) /* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH BIT(17) /* LED pin high */
+
int board_early_init_f(void)
{
/*
return 0;
}
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
int board_init(void)
{
/*
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
-
#if CONFIG_IS_ENABLED(BOOTSTAGE)
-#define GREEN_LED (1 << 14)
-#define ORANGE_LED (1 << 15)
+#define GREEN_LED BIT(14)
+#define ORANGE_LED BIT(15)
#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
#define NEITHER_LED 0
static void set_leds(u32 leds, u32 blinking)
{
struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
- u32 oe = readl(&r->oe) | BOTH_LEDS;
+ u32 oe;
+ u32 bl;
+
+ oe = readl(&r->oe) | BOTH_LEDS;
writel(oe & ~leds, &r->oe); /* active low */
- u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ bl = readl(&r->blink_en) & ~BOTH_LEDS;
writel(bl | blinking, &r->blink_en);
}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
- *
- * Based on sheevaplug.h originally written by
- * Prafulla Wadaskar <prafulla@marvell.com>
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __DOCKSTAR_H
-#define __DOCKSTAR_H
-
-#define DOCKSTAR_OE_LOW (~(0))
-#define DOCKSTAR_OE_HIGH (~(0))
-#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
-#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DOCKSTAR_H */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.h originally written by
#include "mv-common.h"
/*
- * Environment variables configurations
- */
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-
-/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT \
"kernel=/boot/uImage\0" \
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
/*
* Ethernet Driver configuration
*/
-#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * File system
- */
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
+#endif
#endif /* _CONFIG_DOCKSTAR_H */