memory: tegra: Correct la.reg address of seswr

According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 7fb8b54..0888142 100644 (file)
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
                        .bit = 1,
                },
                .la = {
-                       .reg = 0xb98,
+                       .reg = 0x3e0,
                        .shift = 16,
                        .mask = 0xff,
                        .def = 0x80,