[ARM] Fix the decoding of indexed element VCMLA instruction

Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset.  This could cause incorrect disassembly of some
currently undefined instructions as vcmla.

Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).

opcodes/
	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

gas/
	* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
	* testsuite/gas/arm/armv8_3-a-simd.d: Update.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9569b4b..a4ee544 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
+       * testsuite/gas/arm/armv8_3-a-simd.d: Update.
+
 2017-01-18  Bernhard Rosenkranzer  <bero@lindev.ch>
 
        PR 21059

diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.d b/gas/testsuite/gas/arm/armv8_3-a-simd.d
index c420cff..356b5a6 100644 (file)
--- a/gas/testsuite/gas/arm/armv8_3-a-simd.d
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.d
@@ -25,6 +25,12 @@ Disassembly of section .text:
  +[0-9a-f]+:   fe142863        vcmla.f16       q1, q2, d3\[1\], #90
  +[0-9a-f]+:   fed658a7        vcmla.f32       d21, d22, d23\[0\], #90
  +[0-9a-f]+:   fe942867        vcmla.f32       q1, q2, d23\[0\], #90
+ +[0-9a-f]+:   fe042863        vcmla.f16       q1, q2, d3\[1\], #0
+ +[0-9a-f]+:   fe242863        vcmla.f16       q1, q2, d3\[1\], #180
+ +[0-9a-f]+:   fe342863        vcmla.f16       q1, q2, d3\[1\], #270
+ +[0-9a-f]+:   fe842843        vcmla.f32       q1, q2, d3\[0\], #0
+ +[0-9a-f]+:   fea42843        vcmla.f32       q1, q2, d3\[0\], #180
+ +[0-9a-f]+:   feb42843        vcmla.f32       q1, q2, d3\[0\], #270
 
 [0-9a-f]+ <.*>:
  +[0-9a-f]+:   fc94 2846       vcadd.f32       q1, q2, q3, #90
@@ -45,3 +51,9 @@ Disassembly of section .text:
  +[0-9a-f]+:   fe14 2863       vcmla.f16       q1, q2, d3\[1\], #90
  +[0-9a-f]+:   fed6 58a7       vcmla.f32       d21, d22, d23\[0\], #90
  +[0-9a-f]+:   fe94 2867       vcmla.f32       q1, q2, d23\[0\], #90
+ +[0-9a-f]+:   fe04 2863       vcmla.f16       q1, q2, d3\[1\], #0
+ +[0-9a-f]+:   fe24 2863       vcmla.f16       q1, q2, d3\[1\], #180
+ +[0-9a-f]+:   fe34 2863       vcmla.f16       q1, q2, d3\[1\], #270
+ +[0-9a-f]+:   fe84 2843       vcmla.f32       q1, q2, d3\[0\], #0
+ +[0-9a-f]+:   fea4 2843       vcmla.f32       q1, q2, d3\[0\], #180
+ +[0-9a-f]+:   feb4 2843       vcmla.f32       q1, q2, d3\[0\], #270

diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.s b/gas/testsuite/gas/arm/armv8_3-a-simd.s
index fde2f76..4ff5817 100644 (file)
--- a/gas/testsuite/gas/arm/armv8_3-a-simd.s
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.s
@@ -24,6 +24,13 @@ A1:
        vcmla.f32 d21,d22,d23[0],#90
        vcmla.f32 q1,q2,d23[0],#90
 
+       vcmla.f16 q1,q2,d3[1],#0
+       vcmla.f16 q1,q2,d3[1],#180
+       vcmla.f16 q1,q2,d3[1],#270
+       vcmla.f32 q1,q2,d3[0],#0
+       vcmla.f32 q1,q2,d3[0],#180
+       vcmla.f32 q1,q2,d3[0],#270
+
 T1:
        .thumb
 
@@ -47,3 +54,10 @@ T1:
        vcmla.f16 q1,q2,d3[1],#90
        vcmla.f32 d21,d22,d23[0],#90
        vcmla.f32 q1,q2,d23[0],#90
+
+       vcmla.f16 q1,q2,d3[1],#0
+       vcmla.f16 q1,q2,d3[1],#180
+       vcmla.f16 q1,q2,d3[1],#270
+       vcmla.f32 q1,q2,d3[0],#0
+       vcmla.f32 q1,q2,d3[0],#180
+       vcmla.f32 q1,q2,d3[0],#270

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d4f35bd..5a98859 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
+
 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 
        * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 167c668..2987403 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -897,13 +897,13 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
+    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
+    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 
   /* V5 coprocessor instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),