* config/pa/fptr.c: Fix comment typos.
* config/pa/pa-64.h: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/rs6000/603.md: Likewise.
* config/rs6000/7xx.md: Likewise.
* config/rs6000/darwin.h: Likewise.
* config/rs6000/freebsd.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rs6000/rs6000.md: Likewise.
* config/rs6000/spe.h: Likewise.
From-SVN: r68947
+2003-07-04 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/pa/fptr.c: Fix comment typos.
+ * config/pa/pa-64.h: Likewise.
+ * config/pa/pa.c: Likewise.
+ * config/pa/pa.h: Likewise.
+ * config/rs6000/603.md: Likewise.
+ * config/rs6000/7xx.md: Likewise.
+ * config/rs6000/darwin.h: Likewise.
+ * config/rs6000/freebsd.h: Likewise.
+ * config/rs6000/rs6000.c: Likewise.
+ * config/rs6000/rs6000.md: Likewise.
+ * config/rs6000/spe.h: Likewise.
+
2003-07-04 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/2064.md: Change GNU CC to GCC.
/* Find the first "bl" branch in the offset search list. This is a
call to fixup or a magic branch to fixup at the beginning of the
trampoline template. The fixup function does the actual runtime
- resolution of function decriptors. We only look for "bl" branches
+ resolution of function descriptors. We only look for "bl" branches
with a 17-bit pc-relative displacement. */
for (i = 0; i < NOFFSETS; i++)
{
next argument, if that argument is smaller than its aligned space as
controlled by PARM_BOUNDARY. If this macro is not defined, all such
arguments are padded down when BYTES_BIG_ENDIAN is true. We don't
- want aggregrates padded down. */
+ want aggregates padded down. */
#define PAD_VARARGS_DOWN (!AGGREGATE_TYPE_P (type))
normally.
Note SCRATCH_REG may not be in the proper mode depending on how it
- will be used. This routine is resposible for creating a new copy
+ will be used. This routine is responsible for creating a new copy
of SCRATCH_REG in the proper mode. */
int
return (decl != NULL_TREE);
/* Sibcalls are not ok because the arg pointer register is not a fixed
- register. This prevents the sibcall optimization from occuring. In
+ register. This prevents the sibcall optimization from occurring. In
addition, there are problems with stub placement using GNU ld. This
is because a normal sibcall branch uses a 17-bit relocation while
a regular call branch uses a 22-bit relocation. As a result, more
This is magic. Normally, using a PARALLEL results in left
justified data on a big-endian target. However, using a
single double-word register provides the required right
- justication for 5 to 8 byte structures. This has nothing
+ justification for 5 to 8 byte structures. This has nothing
to do with the direction of padding specified for the argument.
It has to do with how the data is widened and shifted into
and from the register.
difference calls. This is a call variant similar to the long pic
pc-relative call. Long pic symbol difference calls are only used with
the HP SOM linker. Currently, only the HP assembler supports these
- calls. GAS doesn't allow an arbritrary difference of two symbols. */
+ calls. GAS doesn't allow an arbitrary difference of two symbols. */
#define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
/* Define to a C expression evaluating to true to use long pic
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them; separation by more than 9 insns ensures that the CR
;; bits will be immediately available for execution.
-;; This could be artificially achieved by exagerating the latency of
+;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; CR insns get executed in the SRU. Not modelled.
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them. There is no advantage have more than 10 cycles
;; of separation.
-;; This could be artificially achieved by exagerating the latency of
+;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; Branches go straight to the BPU. All other insns are handled
#define PROCESSOR_DEFAULT PROCESSOR_PPC7400
/* Default target flag settings. Despite the fact that STMW/LMW
- serializes, it's still a big codesize win to use them. Use FSEL by
+ serializes, it's still a big code size win to use them. Use FSEL by
default as well. */
#undef TARGET_DEFAULT
#define LINK_OS_DEFAULT_SPEC "%(link_os_freebsd)"
/* XXX: This is wrong for many platforms in sysv4.h.
- We should work on getting that defination fixed. */
+ We should work on getting that definition fixed. */
#undef LINK_SHLIB_SPEC
#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
/* Vector constant 0 is handled as a splitter of V2SI, and in the
pattern of V1DI, V4HI, and V2SF.
- FIXME: We should probabl return # and add post reload
+ FIXME: We should probably return # and add post reload
splitters for these, but this way is so easy ;-).
*/
operands[1] = GEN_INT (cst);
/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
to perform a left shift. It must have SHIFTOP or more least
- signifigant 0's, with the remainder of the word 1's. */
+ significant 0's, with the remainder of the word 1's. */
int
includes_rldicr_lshift_p (shiftop, andop)
shift_mask <<= INTVAL (shiftop);
c = INTVAL (andop);
- /* Find the least signifigant one bit. */
+ /* Find the least significant one bit. */
lsb = c & -c;
/* It must be covered by the shift mask.
return set;
}
-/* This retuns nonzero if the current function uses the TOC. This is
+/* This returns nonzero if the current function uses the TOC. This is
determined by the presence of (unspec ... UNSPEC_TOC) or
use (unspec ... UNSPEC_TOC), which are generated by the various
load_toc_* patterns. */
"HAVE_AS_TLS && TARGET_64BIT"
"addi %0,%1,%2@tprel@l")
-;; "b" output contraint here and on tls_tls input to support linker tls
+;; "b" output constraint here and on tls_tls input to support linker tls
;; optimization. The linker may edit the instructions emitted by a
;; tls_got_tprel/tls_tls pair to addis,addi.
(define_insn "tls_got_tprel_32"
#define __ev_lower_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_lower, (a), (b))
#define __ev_select_fs_tst_eq __builtin_spe_evsel_fststeq
-/* SPEFSCR accesor functions. */
+/* SPEFSCR accessor functions. */
#define __SPEFSCR_SOVH 0x80000000
#define __SPEFSCR_OVH 0x40000000
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