drm/amd/pp: fix the wrong readout engine clock in deep sleep
authorEvan Quan <evan.quan@amd.com>
Tue, 10 Apr 2018 05:05:49 +0000 (13:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 May 2018 18:43:04 +0000 (13:43 -0500)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h

index f6427c8..c90502b 100644 (file)
@@ -3805,7 +3805,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
                              void *value, int *size)
 {
        struct amdgpu_device *adev = hwmgr->adev;
-       uint32_t sclk_idx, mclk_idx, activity_percent = 0;
+       uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
        struct vega10_hwmgr *data = hwmgr->backend;
        struct vega10_dpm_table *dpm_table = &data->dpm_table;
        int ret = 0;
@@ -3813,14 +3813,9 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 
        switch (idx) {
        case AMDGPU_PP_SENSOR_GFX_SCLK:
-               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
-               sclk_idx = smum_get_argument(hwmgr);
-               if (sclk_idx <  dpm_table->gfx_table.count) {
-                       *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
-                       *size = 4;
-               } else {
-                       ret = -EINVAL;
-               }
+               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
+               sclk_mhz = smum_get_argument(hwmgr);
+               *((uint32_t *)value) = sclk_mhz * 100;
                break;
        case AMDGPU_PP_SENSOR_GFX_MCLK:
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
index c3ed737..715b5a1 100644 (file)
@@ -131,6 +131,7 @@ typedef uint16_t PPSMC_Result;
 #define PPSMC_MSG_RunAcgInOpenLoop               0x5E
 #define PPSMC_MSG_InitializeAcg                  0x5F
 #define PPSMC_MSG_GetCurrPkgPwr                  0x61
+#define PPSMC_MSG_GetAverageGfxclkActualFrequency 0x63
 #define PPSMC_MSG_SetPccThrottleLevel            0x67
 #define PPSMC_MSG_UpdatePkgPwrPidAlpha           0x68
 #define PPSMC_Message_Count                      0x69