* +--------------------+
*/
-struct overlay_cache_data {
+struct ovl_priv_data {
/* If true, cache changed, but not written to shadow registers. Set
* in apply(), cleared when registers written. */
bool dirty;
static struct {
spinlock_t lock;
- struct overlay_cache_data overlay_cache[MAX_DSS_OVERLAYS];
+ struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
struct manager_cache_data manager_cache[MAX_DSS_MANAGERS];
bool irq_enabled;
} dss_cache;
+static struct ovl_priv_data *get_ovl_priv(struct omap_overlay *ovl)
+{
+ return &dss_cache.ovl_priv_data_array[ovl->id];
+}
+
void dss_apply_init(void)
{
spin_lock_init(&dss_cache.lock);
int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
{
unsigned long timeout = msecs_to_jiffies(500);
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
struct omap_dss_device *dssdev;
u32 irq;
int r;
irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
- oc = &dss_cache.overlay_cache[ovl->id];
+ op = get_ovl_priv(ovl);
i = 0;
while (1) {
unsigned long flags;
bool shadow_dirty, dirty;
spin_lock_irqsave(&dss_cache.lock, flags);
- dirty = oc->dirty;
- shadow_dirty = oc->shadow_dirty;
+ dirty = op->dirty;
+ shadow_dirty = op->shadow_dirty;
spin_unlock_irqrestore(&dss_cache.lock, flags);
if (!dirty && !shadow_dirty) {
static int dss_ovl_write_regs(struct omap_overlay *ovl)
{
- struct overlay_cache_data *c;
+ struct ovl_priv_data *op;
struct omap_overlay_info *oi;
bool ilace, replication;
int r;
DSSDBGF("%d", ovl->id);
- c = &dss_cache.overlay_cache[ovl->id];
- oi = &c->info;
+ op = get_ovl_priv(ovl);
+ oi = &op->info;
- if (!c->enabled) {
+ if (!op->enabled) {
dispc_ovl_enable(ovl->id, 0);
return 0;
}
ilace = ovl->manager->device->type == OMAP_DISPLAY_TYPE_VENC;
- dispc_ovl_set_channel_out(ovl->id, c->channel);
+ dispc_ovl_set_channel_out(ovl->id, op->channel);
r = dispc_ovl_setup(ovl->id, oi, ilace, replication);
if (r) {
return r;
}
- dispc_ovl_set_fifo_threshold(ovl->id, c->fifo_low, c->fifo_high);
+ dispc_ovl_set_fifo_threshold(ovl->id, op->fifo_low, op->fifo_high);
dispc_ovl_enable(ovl->id, 1);
{
struct omap_overlay *ovl;
struct omap_overlay_manager *mgr;
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
struct manager_cache_data *mc;
const int num_ovls = dss_feat_get_num_ovls();
const int num_mgrs = dss_feat_get_num_mgrs();
/* Commit overlay settings */
for (i = 0; i < num_ovls; ++i) {
ovl = omap_dss_get_overlay(i);
- oc = &dss_cache.overlay_cache[i];
- mc = &dss_cache.manager_cache[oc->channel];
+ op = get_ovl_priv(ovl);
+ mc = &dss_cache.manager_cache[op->channel];
- if (!oc->dirty)
+ if (!op->dirty)
continue;
if (mc->manual_update && !mc->do_manual_update)
continue;
- if (mgr_busy[oc->channel]) {
+ if (mgr_busy[op->channel]) {
busy = true;
continue;
}
if (r)
DSSERR("dss_ovl_write_regs %d failed\n", i);
- oc->dirty = false;
- oc->shadow_dirty = true;
- mgr_go[oc->channel] = true;
+ op->dirty = false;
+ op->shadow_dirty = true;
+ mgr_go[op->channel] = true;
}
/* Commit manager settings */
void dss_mgr_start_update(struct omap_overlay_manager *mgr)
{
struct manager_cache_data *mc;
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
struct omap_overlay *ovl;
mc = &dss_cache.manager_cache[mgr->id];
mc->do_manual_update = false;
list_for_each_entry(ovl, &mgr->overlays, list) {
- oc = &dss_cache.overlay_cache[ovl->id];
- oc->shadow_dirty = false;
+ op = get_ovl_priv(ovl);
+ op->shadow_dirty = false;
}
mc = &dss_cache.manager_cache[mgr->id];
static void dss_apply_irq_handler(void *data, u32 mask)
{
+ struct omap_overlay *ovl;
struct manager_cache_data *mc;
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
const int num_ovls = dss_feat_get_num_ovls();
const int num_mgrs = dss_feat_get_num_mgrs();
int i, r;
spin_lock(&dss_cache.lock);
for (i = 0; i < num_ovls; ++i) {
- oc = &dss_cache.overlay_cache[i];
- if (!mgr_busy[oc->channel])
- oc->shadow_dirty = false;
+ ovl = omap_dss_get_overlay(i);
+ op = get_ovl_priv(ovl);
+ if (!mgr_busy[op->channel])
+ op->shadow_dirty = false;
}
for (i = 0; i < num_mgrs; ++i) {
static int omap_dss_mgr_apply_ovl(struct omap_overlay *ovl)
{
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
struct omap_dss_device *dssdev;
- oc = &dss_cache.overlay_cache[ovl->id];
+ op = get_ovl_priv(ovl);
if (ovl->manager_changed) {
ovl->manager_changed = false;
}
if (!overlay_enabled(ovl)) {
- if (oc->enabled) {
- oc->enabled = false;
- oc->dirty = true;
+ if (op->enabled) {
+ op->enabled = false;
+ op->dirty = true;
}
return 0;
}
dssdev = ovl->manager->device;
if (dss_check_overlay(ovl, dssdev)) {
- if (oc->enabled) {
- oc->enabled = false;
- oc->dirty = true;
+ if (op->enabled) {
+ op->enabled = false;
+ op->dirty = true;
}
return -EINVAL;
}
ovl->info_dirty = false;
- oc->dirty = true;
- oc->info = ovl->info;
+ op->dirty = true;
+ op->info = ovl->info;
- oc->channel = ovl->manager->id;
+ op->channel = ovl->manager->id;
- oc->enabled = true;
+ op->enabled = true;
return 0;
}
static void omap_dss_mgr_apply_ovl_fifos(struct omap_overlay *ovl)
{
- struct overlay_cache_data *oc;
+ struct ovl_priv_data *op;
struct omap_dss_device *dssdev;
u32 size, burst_size;
- oc = &dss_cache.overlay_cache[ovl->id];
+ op = get_ovl_priv(ovl);
- if (!oc->enabled)
+ if (!op->enabled)
return;
dssdev = ovl->manager->device;
case OMAP_DISPLAY_TYPE_VENC:
case OMAP_DISPLAY_TYPE_HDMI:
default_get_overlay_fifo_thresholds(ovl->id, size,
- burst_size, &oc->fifo_low,
- &oc->fifo_high);
+ burst_size, &op->fifo_low,
+ &op->fifo_high);
break;
#ifdef CONFIG_OMAP2_DSS_DSI
case OMAP_DISPLAY_TYPE_DSI:
dsi_get_overlay_fifo_thresholds(ovl->id, size,
- burst_size, &oc->fifo_low,
- &oc->fifo_high);
+ burst_size, &op->fifo_low,
+ &op->fifo_high);
break;
#endif
default: