mmc: clarify DDR timing mode between SD-UHS and eMMC

This change distinguishes DDR timing mode of current
mixed usage to clarify device type.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 79f7ae7c45a6ccf04e2908337461dee615f6afb0)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index 54829c0..509229b 100644 (file)
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data)
        case MMC_TIMING_UHS_DDR50:
                str = "sd uhs DDR50";
                break;
+       case MMC_TIMING_MMC_DDR52:
+               str = "mmc DDR52";
+               break;
        case MMC_TIMING_MMC_HS200:
                str = "mmc high-speed SDR200";
                break;

diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 98e9eb0..6d91ff7 100644 (file)
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1261,7 +1261,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
                                        goto err;
                        }
                        mmc_card_set_ddr_mode(card);
-                       mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50);
+                       mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52);
                        mmc_set_bus_width(card->host, bus_width);
                }
        }

diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 99f5709..87b1f4f 100644 (file)
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -58,7 +58,8 @@ struct mmc_ios {
 #define MMC_TIMING_UHS_SDR50   5
 #define MMC_TIMING_UHS_SDR104  6
 #define MMC_TIMING_UHS_DDR50   7
-#define MMC_TIMING_MMC_HS200   8
+#define MMC_TIMING_MMC_DDR52   8
+#define MMC_TIMING_MMC_HS200   9
 
 #define MMC_SDR_MODE           0
 #define MMC_1_2V_DDR_MODE      1