};
static inline void _radeon_bo_debug(struct radeon_bo *bo,
- int opcode,
+ const char *op,
const char *file,
const char *func,
int line)
{
- fprintf(stderr, "%02d %p 0x%08X 0x%08X 0x%08X [%s %s %d]\n",
- opcode, bo, bo->handle, bo->size, bo->cref, file, func, line);
+ fprintf(stderr, "%s %p 0x%08X 0x%08X 0x%08X [%s %s %d]\n",
+ op, bo, bo->handle, bo->size, bo->cref, file, func, line);
}
static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom,
open_arg.name = handle;
r = ioctl(bom->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
if (r != 0) {
- fprintf(stderr, "GEM open failed: %d (%s)\n",r,strerror(r));
free(bo);
return NULL;
}
args.alignment = alignment;
args.initial_domain = bo->base.domains;
args.no_backing_store = 0;
+ args.handle = 0;
r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
&args, sizeof(args));
bo->base.handle = args.handle;
/* close object */
args.handle = bo->handle;
ioctl(bo->bom->fd, DRM_IOCTL_GEM_CLOSE, &args);
+ memset(bo_gem, 0, sizeof(struct radeon_bo_gem));
free(bo_gem);
return NULL;
}
unsigned i;
int r;
+ csg->chunks[0].length_dw = cs->cdw;
+
chunk_array[0] = (uint64_t)(intptr_t)&csg->chunks[0];
chunk_array[1] = (uint64_t)(intptr_t)&csg->chunks[1];
static int cs_gem_need_flush(struct radeon_cs *cs)
{
- return (cs->relocs_total_size > (16*1024*1024));
+ return (cs->relocs_total_size > (32*1024*1024));
+}
+
+#define PACKET_TYPE0 0
+#define PACKET_TYPE1 1
+#define PACKET_TYPE2 2
+#define PACKET_TYPE3 3
+
+#define PACKET3_NOP 0x10
+#define PACKET3_SET_SCISSORS 0x1E
+#define PACKET3_3D_DRAW_VBUF 0x28
+#define PACKET3_3D_DRAW_IMMD 0x29
+#define PACKET3_3D_DRAW_INDX 0x2A
+#define PACKET3_3D_LOAD_VBPNTR 0x2F
+#define PACKET3_INDX_BUFFER 0x33
+#define PACKET3_3D_DRAW_VBUF_2 0x34
+#define PACKET3_3D_DRAW_IMMD_2 0x35
+#define PACKET3_3D_DRAW_INDX_2 0x36
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+static void cs_gem_print(struct radeon_cs *cs, FILE *file)
+{
+ unsigned opcode;
+ unsigned reg;
+ unsigned cnt;
+ int i, j;
+
+ for (i = 0; i < cs->cdw;) {
+ cnt = CP_PACKET_GET_COUNT(cs->packets[i]);
+ switch (CP_PACKET_GET_TYPE(cs->packets[i])) {
+ case PACKET_TYPE0:
+ fprintf(file, "Pkt0 at %d (%d dwords):\n", i, cnt + 1);
+ reg = CP_PACKET0_GET_REG(cs->packets[i]);
+ if (CP_PACKET0_GET_ONE_REG_WR(cs->packets[i++])) {
+ for (j = 0; j <= cnt; j++) {
+ fprintf(file, " 0x%08X -> 0x%04X\n",
+ cs->packets[i++], reg);
+ }
+ } else {
+ for (j = 0; j <= cnt; j++) {
+ fprintf(file, " 0x%08X -> 0x%04X\n",
+ cs->packets[i++], reg);
+ reg += 4;
+ }
+ }
+ break;
+ case PACKET_TYPE3:
+ fprintf(file, "Pkt3 at %d :\n", i);
+ opcode = CP_PACKET3_GET_OPCODE(cs->packets[i++]);
+ switch (opcode) {
+ case PACKET3_NOP:
+ fprintf(file, " PACKET3_NOP:\n");
+ break;
+ case PACKET3_3D_DRAW_VBUF:
+ fprintf(file, " PACKET3_3D_DRAW_VBUF:\n");
+ break;
+ case PACKET3_3D_DRAW_IMMD:
+ fprintf(file, " PACKET3_3D_DRAW_IMMD:\n");
+ break;
+ case PACKET3_3D_DRAW_INDX:
+ fprintf(file, " PACKET3_3D_DRAW_INDX:\n");
+ break;
+ case PACKET3_3D_LOAD_VBPNTR:
+ fprintf(file, " PACKET3_3D_LOAD_VBPNTR:\n");
+ break;
+ case PACKET3_INDX_BUFFER:
+ fprintf(file, " PACKET3_INDX_BUFFER:\n");
+ break;
+ case PACKET3_3D_DRAW_VBUF_2:
+ fprintf(file, " PACKET3_3D_DRAW_VBUF_2:\n");
+ break;
+ case PACKET3_3D_DRAW_IMMD_2:
+ fprintf(file, " PACKET3_3D_DRAW_IMMD_2:\n");
+ break;
+ case PACKET3_3D_DRAW_INDX_2:
+ fprintf(file, " PACKET3_3D_DRAW_INDX_2:\n");
+ break;
+ default:
+ fprintf(file, "Unknow opcode 0x%02X at %d\n", opcode, i);
+ return;
+ }
+ for (j = 0; j <= cnt; j++) {
+ fprintf(file, " 0x%08X\n", cs->packets[i++]);
+ }
+ break;
+ case PACKET_TYPE1:
+ case PACKET_TYPE2:
+ default:
+ fprintf(file, "Unknow packet 0x%08X at %d\n", cs->packets[i], i);
+ return;
+ }
+ }
}
static struct radeon_cs_funcs radeon_cs_gem_funcs = {
cs_gem_emit,
cs_gem_destroy,
cs_gem_erase,
- cs_gem_need_flush
+ cs_gem_need_flush,
+ cs_gem_print
};
struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)