/// Map a register pair Reg to the subregister that has the greater "number",
/// i.e. D3 (aka R7:6) will be mapped to R7, etc.
-static unsigned getMax32BitSubRegister(unsigned Reg,
+static Register getMax32BitSubRegister(Register Reg,
const TargetRegisterInfo &TRI,
bool hireg = true) {
if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
return Reg;
- unsigned RegNo = 0;
+ Register RegNo = 0;
for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
if (hireg) {
if (*SubRegs > RegNo)
}
/// Returns the callee saved register with the largest id in the vector.
-static unsigned getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,
+static Register getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,
const TargetRegisterInfo &TRI) {
static_assert(Hexagon::R1 > 0,
"Assume physical registers are encoded as positive integers");
if (CSI.empty())
return 0;
- unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
+ Register Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
- unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
+ Register Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
if (Reg > Max)
Max = Reg;
}
// Get the number of bytes to allocate from the FrameInfo.
unsigned NumBytes = MFI.getStackSize();
- unsigned SP = HRI.getStackRegister();
+ Register SP = HRI.getStackRegister();
unsigned MaxCF = MFI.getMaxCallFrameSize();
MachineBasicBlock::iterator InsertPt = MBB.begin();
break;
}
- unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
+ Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
: Hexagon::R6;
int LoadStoreCount = ObjSize / OpcodeChecker;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
- unsigned SP = HRI.getStackRegister();
+ Register SP = HRI.getStackRegister();
MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();
DebugLoc dl = MBB.findDebugLoc(InsertPt);
MachineMemOperand::MOStore, 4, Align(4));
DebugLoc dl = MBB.findDebugLoc(InsertPt);
- unsigned SP = HRI.getStackRegister();
+ Register SP = HRI.getStackRegister();
if (NumBytes >= ALLOCFRAME_MAX) {
// Emit allocframe(#0).
.addMemOperand(MMO);
// Subtract the size from the stack pointer.
- unsigned SP = HRI.getStackRegister();
+ Register SP = HRI.getStackRegister();
BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
.addReg(SP)
.addImm(-int(NumBytes));
.addCFIIndex(MF.addFrameInst(OffR30));
}
- static unsigned int RegsToMove[] = {
+ static Register RegsToMove[] = {
Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
- unsigned Reg = RegsToMove[i];
+ Register Reg = RegsToMove[i];
auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
return C.getReg() == Reg;
};
SK_FromMemTailcall
};
-static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
+static const char *getSpillFunctionFor(Register MaxReg, SpillKind SpillType,
bool Stkchk = false) {
const char * V4SpillToMemoryFunctions[] = {
"__save_r16_through_r17",
if (useSpillFunction(MF, CSI)) {
PrologueStubs = true;
- unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
+ Register MaxReg = getMaxCalleeSavedReg(CSI, HRI);
bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
StkOvrFlowEnabled);
if (useRestoreFunction(MF, CSI)) {
bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
- unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
+ Register MaxR = getMaxCalleeSavedReg(CSI, HRI);
SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;
const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
}
// Set the physical aligned-stack base address register.
- unsigned AP = 0;
+ Register AP = 0;
if (const MachineInstr *AI = getAlignaInstr(MF))
AP = AI->getOperand(0).getReg();
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
MachineRegisterInfo &MRI = MF.getRegInfo();
- auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
+ auto IsUsed = [&HRI,&MRI] (Register Reg) -> bool {
for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
if (MRI.isPhysRegUsed(*AI))
return true;
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
dbgs() << '{';
for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
- unsigned R = x;
+ Register R = x;
dbgs() << ' ' << printReg(R, &TRI);
}
dbgs() << " }";
// sub- and super-registers from SRegs.
BitVector Reserved = TRI->getReservedRegs(MF);
for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
- unsigned R = x;
+ Register R = x;
for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
SRegs[*SR] = false;
}
// (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
- unsigned R = x;
+ Register R = x;
for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
TmpSup[*SR] = true;
}
for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
- unsigned R = x;
+ Register R = x;
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
if (!Reserved[*SR])
continue;
// (5) For each register R in SRegs, if any super-register of R is in SRegs,
// remove R from SRegs.
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
- unsigned R = x;
+ Register R = x;
for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
if (!SRegs[*SR])
continue;
// we need to store R0-R3 in functions with exception handling. For each
// such register, create a non-fixed stack object.
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
- unsigned R = x;
+ Register R = x;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
unsigned Size = TRI->getSpillSize(*RC);
int Off = MinOffset - Size;
// Verify that all registers were handled.
bool MissedReg = false;
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
- unsigned R = x;
+ Register R = x;
dbgs() << printReg(R, TRI) << ' ';
MissedReg = true;
}
bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineInstr *MI = &*It;
DebugLoc DL = MI->getDebugLoc();
Register DstR = MI->getOperand(0).getReg();
bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineInstr *MI = &*It;
if (!MI->getOperand(0).isFI())
return false;
bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineInstr *MI = &*It;
if (!MI->getOperand(1).isFI())
return false;
bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineInstr *MI = &*It;
if (!MI->getOperand(0).isFI())
return false;
bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineInstr *MI = &*It;
if (!MI->getOperand(1).isFI())
return false;
bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineFunction &MF = *B.getParent();
auto &MFI = MF.getFrameInfo();
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineFunction &MF = *B.getParent();
auto &MFI = MF.getFrameInfo();
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineFunction &MF = *B.getParent();
auto &MFI = MF.getFrameInfo();
MachineInstr *MI = &*It;
bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
- const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
+ const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
MachineFunction &MF = *B.getParent();
auto &MFI = MF.getFrameInfo();
MachineInstr *MI = &*It;
}
bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
- SmallVectorImpl<unsigned> &NewRegs) const {
+ SmallVectorImpl<Register> &NewRegs) const {
auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
bool Changed = false;
SavedRegs.set(*R);
// Replace predicate register pseudo spill code.
- SmallVector<unsigned,8> NewRegs;
+ SmallVector<Register,8> NewRegs;
expandSpillMacros(MF, NewRegs);
if (OptimizeSpillSlots && !isOptNone(MF))
optimizeSpillSlots(MF, NewRegs);
// the stack offset in case it does not fit into a spill instruction.
SpillRCs.insert(&Hexagon::IntRegsRegClass);
- for (unsigned VR : NewRegs)
+ for (Register VR : NewRegs)
SpillRCs.insert(MRI.getRegClass(VR));
for (const auto *RC : SpillRCs) {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
}
-unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
+Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,
HexagonBlockRanges::IndexRange &FIR,
HexagonBlockRanges::InstrIndexMap &IndexMap,
HexagonBlockRanges::RegToRangeMap &DeadMap,
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
auto &MRI = MF.getRegInfo();
- auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
+ auto isDead = [&FIR,&DeadMap] (Register Reg) -> bool {
auto F = DeadMap.find({Reg,0});
if (F == DeadMap.end())
return false;
return false;
};
- for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
+ for (Register Reg : RC->getRawAllocationOrder(MF)) {
bool Dead = true;
for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
if (isDead(R.Reg))
}
void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<unsigned> &VRegs) const {
+ SmallVectorImpl<Register> &VRegs) const {
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
SrcOp.getSubReg() };
auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
// The this-> is needed to unconfuse MSVC.
- unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
+ Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
<< '\n');
if (FoundR == 0)
}
void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
- const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
+ const HexagonInstrInfo &HII, Register SP, unsigned CF) const {
MachineBasicBlock &MB = *AI->getParent();
DebugLoc DL = AI->getDebugLoc();
unsigned A = AI->getOperand(2).getImm();
MachineOperand &RdOp = AI->getOperand(0);
MachineOperand &RsOp = AI->getOperand(1);
- unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
+ Register Rd = RdOp.getReg(), Rs = RsOp.getReg();
// Rd = sub(r29, Rs)
BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
using CSIVect = std::vector<CalleeSavedInfo>;
void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
- unsigned SP, unsigned CF) const;
+ Register SP, unsigned CF) const;
void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
void insertAllocframe(MachineBasicBlock &MBB,
bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
bool expandSpillMacros(MachineFunction &MF,
- SmallVectorImpl<unsigned> &NewRegs) const;
+ SmallVectorImpl<Register> &NewRegs) const;
- unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
+ Register findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
HexagonBlockRanges::InstrIndexMap &IndexMap,
HexagonBlockRanges::RegToRangeMap &DeadMap,
const TargetRegisterClass *RC) const;
void optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<unsigned> &VRegs) const;
+ SmallVectorImpl<Register> &VRegs) const;
void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
MachineBasicBlock *&EpilogB) const;
}
private:
- using LoopFeederMap = std::map<unsigned, MachineInstr *>;
+ using LoopFeederMap = std::map<Register, MachineInstr *>;
/// Kinds of comparisons in the compare instructions.
struct Comparison {
/// if (R.next < #N) goto loop
/// IVBump is the immediate value added to R, and IVOp is the instruction
/// "R.next = R + #bump".
- bool findInductionRegister(MachineLoop *L, unsigned &Reg,
+ bool findInductionRegister(MachineLoop *L, Register &Reg,
int64_t &IVBump, MachineInstr *&IVOp) const;
/// Return the comparison kind for the specified opcode.
/// or a register), the function will attempt to insert computation of it
/// to the loop's preheader.
CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start,
- const MachineOperand *End, unsigned IVReg,
+ const MachineOperand *End, Register IVReg,
int64_t IVBump, Comparison::Kind Cmp) const;
/// Return true if the instruction is not valid within a hardware
private:
CountValueType Kind;
union Values {
+ Values() : R{Register(), 0} {}
+ Values(const Values&) = default;
struct {
- unsigned Reg;
+ Register Reg;
unsigned Sub;
} R;
unsigned ImmVal;
} Contents;
public:
- explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {
+ explicit CountValue(CountValueType t, Register v, unsigned u = 0) {
Kind = t;
if (Kind == CV_Register) {
Contents.R.Reg = v;
bool isReg() const { return Kind == CV_Register; }
bool isImm() const { return Kind == CV_Immediate; }
- unsigned getReg() const {
+ Register getReg() const {
assert(isReg() && "Wrong CountValue accessor");
return Contents.R.Reg;
}
}
bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
- unsigned &Reg,
+ Register &Reg,
int64_t &IVBump,
MachineInstr *&IVOp
) const {
// This pair represents an induction register together with an immediate
// value that will be added to it in each loop iteration.
- using RegisterBump = std::pair<unsigned, int64_t>;
+ using RegisterBump = std::pair<Register, int64_t>;
// Mapping: R.next -> (R, bump), where R, R.next and bump are derived
// from an induction operation
// R.next = R + bump
// where bump is an immediate value.
- using InductionMap = std::map<unsigned, RegisterBump>;
+ using InductionMap = std::map<Register, RegisterBump>;
InductionMap IndMap;
if (NotAnalyzed)
return false;
- unsigned PredR, PredPos, PredRegFlags;
+ Register PredR;
+ unsigned PredPos, PredRegFlags;
if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
return false;
if (!ExitingBlock)
return nullptr;
- unsigned IVReg = 0;
+ Register IVReg = 0;
int64_t IVBump = 0;
MachineInstr *IVOp;
bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
// If TB is not the header, it means that the "not-taken" path must lead
// to the header.
bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
- unsigned PredReg, PredPos, PredRegFlags;
+ Register PredReg;
+ unsigned PredPos, PredRegFlags;
if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
return nullptr;
MachineInstr *CondI = MRI->getVRegDef(PredReg);
CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
const MachineOperand *Start,
const MachineOperand *End,
- unsigned IVReg,
+ Register IVReg,
int64_t IVBump,
Comparison::Kind Cmp) const {
// Cannot handle comparison EQ, i.e. while (A == B).
AdjV += (IVBump-1);
}
- unsigned R = 0, SR = 0;
+ Register R = 0;
+ unsigned SR = 0;
if (Start->isReg()) {
R = Start->getReg();
SR = Start->getSubReg();
const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
// Compute DistR (register with the distance between Start and End).
- unsigned DistR, DistSR;
+ Register DistR;
+ unsigned DistSR;
// Avoid special case, where the start value is an imm(0).
if (Start->isImm() && StartV == 0) {
}
// From DistR, compute AdjR (register with the adjusted distance).
- unsigned AdjR, AdjSR;
+ Register AdjR;
+ unsigned AdjSR;
if (AdjV == 0) {
AdjR = DistR;
}
// From AdjR, compute CountR (register with the final count).
- unsigned CountR, CountSR;
+ Register CountR;
+ unsigned CountSR;
if (IVBump == 1) {
CountR = AdjR;
// Check if the instruction defines a hardware loop register.
using namespace Hexagon;
- static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
- static const unsigned Regs1[] = { LC1, SA1 };
+ static const Register Regs01[] = { LC0, SA0, LC1, SA1 };
+ static const Register Regs1[] = { LC1, SA1 };
auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, std::size(Regs01))
: makeArrayRef(Regs1, std::size(Regs1));
- for (unsigned R : CheckRegs)
+ for (Register R : CheckRegs)
if (MI->modifiesRegister(R, TRI))
return true;
// These data structures follow the same concept as the corresponding
// ones in findInductionRegister (where some comments are).
- using RegisterBump = std::pair<unsigned, int64_t>;
- using RegisterInduction = std::pair<unsigned, RegisterBump>;
+ using RegisterBump = std::pair<Register, int64_t>;
+ using RegisterInduction = std::pair<Register, RegisterBump>;
using RegisterInductionSet = std::set<RegisterInduction>;
// Register candidates for induction variables, with their associated bumps.
if (!PredDef->isCompare())
return false;
- SmallSet<unsigned,2> CmpRegs;
+ SmallSet<Register,2> CmpRegs;
MachineOperand *CmpImmOp = nullptr;
// Go over all operands to the compare and look for immediate and register
}
}
-static bool isIntRegForSubInst(unsigned Reg) {
+static bool isIntRegForSubInst(Register Reg) {
return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
(Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
}
-static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
+static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
}
/// This treats possible (predicated) defs as actually happening ones
/// (conservatively).
static inline void parseOperands(const MachineInstr &MI,
- SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
+ SmallVectorImpl<Register> &Defs, SmallVectorImpl<Register> &Uses) {
Defs.clear();
Uses.clear();
SmallVectorImpl<MachineOperand> &Cond) override {
if (TripCount == -1) {
// Check if we're done with the loop.
- unsigned Done = TII->createVR(MF, MVT::i1);
+ Register Done = TII->createVR(MF, MVT::i1);
MachineInstr *NewCmp = BuildMI(&MBB, DL,
TII->get(Hexagon::C2_cmpgtui), Done)
.addReg(LoopCount)
auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
Register Mx = MI.getOperand(MxOp).getReg();
- unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
+ Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
.add(MI.getOperand((HasImm ? 5 : 4)));
auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
NOp++;
}
- unsigned PredReg, PredRegPos, PredRegFlags;
+ Register PredReg;
+ unsigned PredRegPos, PredRegFlags;
bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
(void)GotPredReg;
assert(GotPredReg);
}
continue;
} else if (MO.isRegMask()) {
- for (unsigned PR : Hexagon::PredRegsRegClass) {
+ for (Register PR : Hexagon::PredRegsRegClass) {
if (!MI.modifiesRegister(PR, &HRI))
continue;
Pred.push_back(MO);
return makeArrayRef(Flags);
}
-unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
+Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetRegisterClass *TRC;
if (VT == MVT::i1) {
return false;
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
- SmallVector<unsigned, 4> DefsA;
- SmallVector<unsigned, 4> DefsB;
- SmallVector<unsigned, 8> UsesA;
- SmallVector<unsigned, 8> UsesB;
+ SmallVector<Register, 4> DefsA;
+ SmallVector<Register, 4> DefsB;
+ SmallVector<Register, 8> UsesA;
+ SmallVector<Register, 8> UsesB;
parseOperands(ProdMI, DefsA, UsesA);
parseOperands(ConsMI, DefsB, UsesB);
}
bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
- unsigned PredReg) const {
+ Register PredReg) const {
for (const MachineOperand &MO : MI.operands()) {
// Predicate register must be explicitly defined.
if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
// If so, return its group. Zero otherwise.
HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
const MachineInstr &MI) const {
- unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
+ Register DstReg, SrcReg, Src1Reg, Src2Reg;
switch (MI.getOpcode()) {
default:
// If so, return its group. Zero otherwise.
HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
const MachineInstr &MI) const {
- unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
+ Register DstReg, SrcReg, Src1Reg, Src2Reg;
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
switch (MI.getOpcode()) {
}
bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
- unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
+ Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
if (Cond.empty())
return false;
assert(Cond.size() == 2);
/// HexagonInstrInfo specifics.
- unsigned createVR(MachineFunction *MF, MVT VT) const;
+ Register createVR(MachineFunction *MF, MVT VT) const;
MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
MachineBasicBlock *TargetBB,
SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
const MachineInstr &ConsMI) const;
bool producesStall(const MachineInstr &MI,
MachineBasicBlock::const_instr_iterator MII) const;
- bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
+ bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
unsigned getMemAccessSize(const MachineInstr &MI) const;
int getMinValue(const MachineInstr &MI) const;
short getNonExtOpcode(const MachineInstr &MI) const;
- bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
+ bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
unsigned &PredRegPos, unsigned &PredRegFlags) const;
short getPseudoInstrPair(const MachineInstr &MI) const;
short getRegForm(const MachineInstr &MI) const;
0/*PC*/, HwMode) {}
-bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
+bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(Register R) const {
return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
}
// If one register is large (HvxWR) and the other is small (HvxVR), then
// coalescing is ok if the large is already live across a function call,
// or if the small one is not.
- unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
- unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
+ Register SmallReg = SmallSrc ? SrcReg : DstReg;
+ Register LargeReg = SmallSrc ? DstReg : SrcReg;
return any_of(LIS.getInterval(LargeReg), HasCall) ||
!any_of(LIS.getInterval(SmallReg), HasCall);
}
}
-unsigned HexagonRegisterInfo::getFrameRegister() const {
+Register HexagonRegisterInfo::getFrameRegister() const {
return Hexagon::R30;
}
-unsigned HexagonRegisterInfo::getStackRegister() const {
+Register HexagonRegisterInfo::getStackRegister() const {
return Hexagon::R29;
}
return &Hexagon::IntRegsRegClass;
}
-unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
+Register HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
return Hexagon::R6;
}
// Debug information queries.
Register getFrameRegister(const MachineFunction &MF) const override;
- unsigned getFrameRegister() const;
- unsigned getStackRegister() const;
+ Register getFrameRegister() const;
+ Register getStackRegister() const;
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
unsigned GenIdx) const;
const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
const TargetRegisterClass *RC) const;
- unsigned getFirstCallerSavedNonParamReg() const;
+ Register getFirstCallerSavedNonParamReg() const;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const override;
- bool isEHReturnCalleeSaveReg(unsigned Reg) const;
+ bool isEHReturnCalleeSaveReg(Register Reg) const;
};
} // end namespace llvm
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