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drm/nve0/fifo: engine intr
author
Ben Skeggs
<bskeggs@redhat.com>
Sun, 23 Feb 2014 13:08:00 +0000
(23:08 +1000)
committer
Ben Skeggs
<bskeggs@redhat.com>
Wed, 26 Mar 2014 04:00:48 +0000
(14:00 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
patch
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diff --git
a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 6853cd2fa6fd1ba67b3b45f03c4c51c1d992a6a8..b60df6bc9965513060fc23170ed495e1b01b8840 100644
(file)
--- a/
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@
-646,6
+646,12
@@
nve0_fifo_intr_pbdma(struct nve0_fifo_priv *priv, int unit)
nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
}
+static void
+nve0_fifo_intr_engine(struct nve0_fifo_priv *priv)
+{
+ nouveau_event_trigger(priv->base.uevent, 0);
+}
+
static void
nve0_fifo_intr(struct nouveau_subdev *subdev)
{
@@
-737,7
+743,7
@@
nve0_fifo_intr(struct nouveau_subdev *subdev)
}
if (stat & 0x80000000) {
- n
ouveau_event_trigger(priv->base.uevent, 0
);
+ n
ve0_fifo_intr_engine(priv
);
nv_wr32(priv, 0x002100, 0x80000000);
stat &= ~0x80000000;
}