ARM: dts: sti: ensure unique unit-address in stih418-clock

Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index e84c476b83ed51e4248ddd75ce542751ae33e59f..e1749e92a2e79524fc1d242724e5de036f3b67aa 100644 (file)
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -32,7 +32,7 @@
                 */
                clockgen-a9@92b0000 {
                        compatible = "st,clkgen-c32";
-                       reg = <0x92b0000 0xffff>;
+                       reg = <0x92b0000 0x10000>;
 
                        clockgen_a9_pll: clockgen-a9-pll {
                                #clock-cells = <1>;
@@ -40,30 +40,29 @@
 
                                clocks = <&clk_sysin>;
                        };
-               };
-
-               /*
-                * ARM CPU related clocks.
-                */
-               clk_m_a9: clk-m-a9@92b0000 {
-                       #clock-cells = <0>;
-                       compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
-                       reg = <0x92b0000 0x10000>;
-
-                       clocks = <&clockgen_a9_pll 0>,
-                                <&clockgen_a9_pll 0>,
-                                <&clk_s_c0_flexgen 13>,
-                                <&clk_m_a9_ext2f_div2>;
 
                        /*
-                        * ARM Peripheral clock for timers
+                        * ARM CPU related clocks.
                         */
-                       arm_periph_clk: clk-m-a9-periphs {
+                       clk_m_a9: clk-m-a9 {
                                #clock-cells = <0>;
-                               compatible = "fixed-factor-clock";
-                               clocks = <&clk_m_a9>;
-                               clock-div = <2>;
-                               clock-mult = <1>;
+                               compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+
+                               clocks = <&clockgen_a9_pll 0>,
+                                        <&clockgen_a9_pll 0>,
+                                        <&clk_s_c0_flexgen 13>,
+                                        <&clk_m_a9_ext2f_div2>;
+
+                               /*
+                                * ARM Peripheral clock for timers
+                                */
+                               arm_periph_clk: clk-m-a9-periphs {
+                                       #clock-cells = <0>;
+                                       compatible = "fixed-factor-clock";
+                                       clocks = <&clk_m_a9>;
+                                       clock-div = <2>;
+                                       clock-mult = <1>;
+                               };
                        };
                };
 
@@ -88,14 +87,6 @@
                        };
                };
 
-               clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
-                       #clock-cells = <1>;
-                       compatible = "st,quadfs-pll";
-                       reg = <0x9103000 0x1000>;
-
-                       clocks = <&clk_sysin>;
-               };
-
                clk_s_c0: clockgen-c@9103000 {
                        compatible = "st,clkgen-c32";
                        reg = <0x9103000 0x1000>;
@@ -114,6 +105,13 @@
                                clocks = <&clk_sysin>;
                        };
 
+                       clk_s_c0_quadfs: clk-s-c0-quadfs {
+                               #clock-cells = <1>;
+                               compatible = "st,quadfs-pll";
+
+                               clocks = <&clk_sysin>;
+                       };
+
                        clk_s_c0_flexgen: clk-s-c0-flexgen {
                                #clock-cells = <1>;
                                compatible = "st,flexgen", "st,flexgen-stih418-c0";
@@ -143,18 +141,17 @@
                        };
                };
 
-               clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
-                       #clock-cells = <1>;
-                       compatible = "st,quadfs-d0";
-                       reg = <0x9104000 0x1000>;
-
-                       clocks = <&clk_sysin>;
-               };
-
                clockgen-d0@9104000 {
                        compatible = "st,clkgen-c32";
                        reg = <0x9104000 0x1000>;
 
+                       clk_s_d0_quadfs: clk-s-d0-quadfs {
+                               #clock-cells = <1>;
+                               compatible = "st,quadfs-d0";
+
+                               clocks = <&clk_sysin>;
+                       };
+
                        clk_s_d0_flexgen: clk-s-d0-flexgen {
                                #clock-cells = <1>;
                                compatible = "st,flexgen", "st,flexgen-stih410-d0";
@@ -167,18 +164,17 @@
                        };
                };
 
-               clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
-                       #clock-cells = <1>;
-                       compatible = "st,quadfs-d2";
-                       reg = <0x9106000 0x1000>;
-
-                       clocks = <&clk_sysin>;
-               };
-
                clockgen-d2@9106000 {
                        compatible = "st,clkgen-c32";
                        reg = <0x9106000 0x1000>;
 
+                       clk_s_d2_quadfs: clk-s-d2-quadfs {
+                               #clock-cells = <1>;
+                               compatible = "st,quadfs-d2";
+
+                               clocks = <&clk_sysin>;
+                       };
+
                        clk_s_d2_flexgen: clk-s-d2-flexgen {
                                #clock-cells = <1>;
                                compatible = "st,flexgen", "st,flexgen-stih418-d2";
@@ -193,18 +189,17 @@
                        };
                };
 
-               clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
-                       #clock-cells = <1>;
-                       compatible = "st,quadfs-d3";
-                       reg = <0x9107000 0x1000>;
-
-                       clocks = <&clk_sysin>;
-               };
-
                clockgen-d3@9107000 {
                        compatible = "st,clkgen-c32";
                        reg = <0x9107000 0x1000>;
 
+                       clk_s_d3_quadfs: clk-s-d3-quadfs {
+                               #clock-cells = <1>;
+                               compatible = "st,quadfs-d3";
+
+                               clocks = <&clk_sysin>;
+                       };
+
                        clk_s_d3_flexgen: clk-s-d3-flexgen {
                                #clock-cells = <1>;
                                compatible = "st,flexgen", "st,flexgen-stih407-d3";