drm/amdgpu: cleanup instance limit on VCN4 v4

Similar to what we did for VCN3 use the job instead of the parser
entity. Cleanup the coding style quite a bit as well.

v2: merge improved application check into this patch
v3: finally fix the check
v4: limit to the correct engine

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 09c89fa..b6f73b8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1591,21 +1591,23 @@ static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
        }
 }
 
-static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p)
+static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
+                               struct amdgpu_job *job)
 {
        struct drm_gpu_scheduler **scheds;
 
        /* The create msg must be in the first IB submitted */
-       if (atomic_read(&p->entity->fence_seq))
+       if (atomic_read(&job->base.entity->fence_seq))
                return -EINVAL;
 
        scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
                [AMDGPU_RING_PRIO_0].sched;
-       drm_sched_entity_modify_sched(p->entity, scheds, 1);
+       drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
        return 0;
 }
 
-static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
+static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
+                           uint64_t addr)
 {
        struct ttm_operation_ctx ctx = { false, false };
        struct amdgpu_bo_va_mapping *map;
@@ -1676,7 +1678,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
                if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
                        continue;
 
-               r = vcn_v4_0_limit_sched(p);
+               r = vcn_v4_0_limit_sched(p, job);
                if (r)
                        goto out;
        }
@@ -1689,32 +1691,34 @@ out:
 #define RADEON_VCN_ENGINE_TYPE_DECODE                                 (0x00000003)
 
 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
-                               struct amdgpu_job *job,
-                               struct amdgpu_ib *ib)
+                                          struct amdgpu_job *job,
+                                          struct amdgpu_ib *ib)
 {
-       struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
-       struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+       struct amdgpu_ring *ring = amdgpu_job_ring(job);
+       struct amdgpu_vcn_decode_buffer *decode_buffer;
+       uint64_t addr;
        uint32_t val;
-       int r = 0;
 
        /* The first instance can decode anything */
        if (!ring->me)
-               return r;
+               return 0;
 
        /* unified queue ib header has 8 double words. */
        if (ib->length_dw < 8)
-               return r;
+               return 0;
 
        val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE
+       if (val != RADEON_VCN_ENGINE_TYPE_DECODE)
+               return 0;
 
-       if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
-               decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10];
+       decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10];
 
-               if (decode_buffer->valid_buf_flag  & 0x1)
-                       r = vcn_v4_0_dec_msg(p, ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
-                                               decode_buffer->msg_buffer_address_lo);
-       }
-       return r;
+       if (!(decode_buffer->valid_buf_flag  & 0x1))
+               return 0;
+
+       addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
+               decode_buffer->msg_buffer_address_lo;
+       return vcn_v4_0_dec_msg(p, job, addr);
 }
 
 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {