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[X86] Correct the itineraries for the dot production instructions.
author
Craig Topper
<craig.topper@intel.com>
Mon, 26 Mar 2018 02:17:15 +0000
(
02:17
+0000)
committer
Craig Topper
<craig.topper@intel.com>
Mon, 26 Mar 2018 02:17:15 +0000
(
02:17
+0000)
llvm-svn: 328471
llvm/lib/Target/X86/X86InstrSSE.td
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diff --git
a/llvm/lib/Target/X86/X86InstrSSE.td
b/llvm/lib/Target/X86/X86InstrSSE.td
index
323e3c6
..
3ea9dd8
100644
(file)
--- a/
llvm/lib/Target/X86/X86InstrSSE.td
+++ b/
llvm/lib/Target/X86/X86InstrSSE.td
@@
-175,7
+175,7
@@
def SSE_DPPD_ITINS : OpndItins<
>;
def SSE_DPPS_ITINS : OpndItins<
- IIC_SSE_DPPS_RR, IIC_SSE_DPP
D
_RM
+ IIC_SSE_DPPS_RR, IIC_SSE_DPP
S
_RM
>;
def DEFAULT_ITINS : OpndItins<
@@
-6503,7
+6503,7
@@
let Predicates = [HasAVX] in {
let ExeDomain = SSEPackedDouble in
defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
VR128, loadv2f64, f128mem, 0,
- SSE_DPP
S
_ITINS>, VEX_4V, VEX_WIG;
+ SSE_DPP
D
_ITINS>, VEX_4V, VEX_WIG;
let ExeDomain = SSEPackedSingle in
defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
VR256, loadv8f32, i256mem, 0,