{
}
+static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0xffffffffffffffff;
+}
+
/* MSDOS compatibility mode FPU exception support */
static qemu_irq ferr_irq;
qemu_irq_lower(ferr_irq);
}
+static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0xffffffffffffffff;
+}
+
/* TSC handling */
uint64_t cpu_get_tsc(CPUX86State *env)
{
static const MemoryRegionOps ioport80_io_ops = {
.write = ioport80_write,
+ .read = ioport80_read,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
static const MemoryRegionOps ioportF0_io_ops = {
.write = ioportF0_write,
+ .read = ioportF0_read,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,