net/mlx5e: MACsec, remove replay window size limitation in offload path
authorEmeel Hakim <ehakim@nvidia.com>
Mon, 31 Oct 2022 09:07:59 +0000 (11:07 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Thu, 24 Nov 2022 08:03:22 +0000 (00:03 -0800)
Currently offload path limits replay window size to 32/64/128/256 bits,
such a limitation should not exist since software allows it.
Remove such limitation.

Fixes: eb43846b43c3 ("net/mlx5e: Support MACsec offload replay window")
Signed-off-by: Emeel Hakim <ehakim@nvidia.com>
Reviewed-by: Raed Salem <raeds@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c
include/linux/mlx5/mlx5_ifc.h

index c19581f1f733a95a1ee10af1c44072de251152d7..72f8be65fa90b2aa94e706e95c746eecf538b560 100644 (file)
@@ -229,22 +229,6 @@ static int macsec_set_replay_protection(struct mlx5_macsec_obj_attrs *attrs, voi
        if (!attrs->replay_protect)
                return 0;
 
-       switch (attrs->replay_window) {
-       case 256:
-               window_sz = MLX5_MACSEC_ASO_REPLAY_WIN_256BIT;
-               break;
-       case 128:
-               window_sz = MLX5_MACSEC_ASO_REPLAY_WIN_128BIT;
-               break;
-       case 64:
-               window_sz = MLX5_MACSEC_ASO_REPLAY_WIN_64BIT;
-               break;
-       case 32:
-               window_sz = MLX5_MACSEC_ASO_REPLAY_WIN_32BIT;
-               break;
-       default:
-               return -EINVAL;
-       }
        MLX5_SET(macsec_aso, aso_ctx, window_size, window_sz);
        MLX5_SET(macsec_aso, aso_ctx, mode, MLX5_MACSEC_ASO_REPLAY_PROTECTION);
 
index 5a4e914e2a6ff39b9aa38ec0054dae7186f70fa3..981fc7dfa40867027eabfa9b74ae709cbe2df427 100644 (file)
@@ -11611,13 +11611,6 @@ enum {
        MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
 };
 
-enum {
-       MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
-       MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
-       MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
-       MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
-};
-
 #define MLX5_MACSEC_ASO_INC_SN  0x2
 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2