PCI: designware: Use exact access size in dw_pcie_cfg_read()

dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size
requested, but dw_pcie_cfg_read() previously performed a 32-bit read and
masked out the bits requested.

Use the exact access size in dw_pcie_cfg_read().  For example, if we want
an 8-bit read, use readb() instead of using readl() and masking out the 8
bits we need.  This makes it symmetric with dw_pcie_cfg_write().

[bhelgaas: split into separate patch, set *val = 0 in failure case]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 0085748..451f01e 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -82,14 +82,16 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
 
 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
-       *val = readl(addr);
-
-       if (size == 1)
-               *val = (*val >> (8 * (where & 3))) & 0xff;
+       if (size == 4)
+               *val = readl(addr);
        else if (size == 2)
-               *val = (*val >> (8 * (where & 3))) & 0xffff;
-       else if (size != 4)
+               *val = readw(addr + (where & 2));
+       else if (size == 1)
+               *val = readb(addr + (where & 1));
+       else {
+               *val = 0;
                return PCIBIOS_BAD_REGISTER_NUMBER;
+       }
 
        return PCIBIOS_SUCCESSFUL;
 }