Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for Linux 4.1.  Most
  noteworthy:

   - Add more Octeon-optimized crypto functions
   - Octeon crypto preemption and locking fixes
   - Little endian support for Octeon
   - Use correct CSR to soft reset Octeons
   - Support LEDs on the Octeon-based DSR-1000N
   - Fix PCI interrupt mapping for the Octeon-based DSR-1000N
   - Mark prom_free_prom_memory() as __init for a number of systems
   - Support for Imagination's Pistachio SOC.  This includes arch and
     CLK bits.  I'd like to merge pinctrl bits later
   - Improve parallelism of csum_partial for certain pipelines
   - Organize DTB files in subdirs like other architectures
   - Implement read_sched_clock for all MIPS platforms other than
     Octeon
   - Massive series of 38 fixes and cleanups for the FPU emulator /
     kernel
   - Further FPU remulator work to support new features.  This sits on a
     separate branch which also has been pulled into the 4.1 KVM branch
   - Clean up and fixes for the SEAD3 eval board; remove unused file
   - Various updates for Netlogic platforms
   - A number of small updates for Loongson 3 platforms
   - Increase the memory limit for ATH79 platforms to 256MB
   - A fair number of fixes and updates for BCM47xx platforms
   - Finish the implementation of XPA support
   - MIPS FDC support.  No, not floppy controller but Fast Debug Channel :)
   - Detect the R16000 used in SGI legacy platforms
   - Fix Kconfig dependencies for the SSB bus support"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
  MIPS: Makefile: Fix MIPS ASE detection code
  MIPS: asm: elf: Set O32 default FPU flags
  MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
  MIPS: Kconfig: Disable SMP/CPS for 64-bit
  MIPS: Hibernate: flush TLB entries earlier
  MIPS: smp-cps: cpu_set FPU mask if FPU present
  MIPS: lose_fpu(): Disable FPU when MSA enabled
  MIPS: ralink: add missing symbol for RALINK_ILL_ACC
  MIPS: ralink: Fix bad config symbol in PCI makefile.
  SSB: fix Kconfig dependencies
  MIPS: Malta: Detect and fix bad memsize values
  Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
  MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
  MIPS: Fix cpu_has_mips_r2_exec_hazard.
  MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
  MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
  MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
  MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
  MIPS: unaligned: Fix regular load/store instruction emulation for EVA
  MIPS: unaligned: Surround load/store macros in do {} while statements
  ...

diff --cc Documentation/kernel-parameters.txt
Simple merge

diff --cc arch/mips/Kconfig
Simple merge

diff --cc arch/mips/Makefile
Simple merge

diff --cc arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 3550725,df6912e..7315cc3
--- 1/arch/mips/cavium-octeon/crypto/octeon-crypto.h
--- 2/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@@ -70,29 -70,29 +70,103 @@@ do {                                                      
        __asm__ __volatile__ (                          \
        "dmtc2 %[rt],0x4047"                            \
        :                                               \
+       : [rt] "d" (cpu_to_be64(value)));               \
+ } while (0)
+ 
+ /*
+  * The value is the final block dword (64-bit).
+  */
+ #define octeon_sha1_start(value)                      \
+ do {                                                  \
+       __asm__ __volatile__ (                          \
+       "dmtc2 %[rt],0x4057"                            \
+       :                                               \
+       : [rt] "d" (value));                            \
+ } while (0)
+ 
+ /*
+  * The value is the final block dword (64-bit).
+  */
+ #define octeon_sha256_start(value)                    \
+ do {                                                  \
+       __asm__ __volatile__ (                          \
+       "dmtc2 %[rt],0x404f"                            \
+       :                                               \
+       : [rt] "d" (value));                            \
++} while (0)
++
++/*
++ * Macros needed to implement SHA512:
++ */
++
++/*
++ * The index can be 0-7.
++ */
++#define write_octeon_64bit_hash_sha512(value, index)  \
++do {                                                  \
++      __asm__ __volatile__ (                          \
++      "dmtc2 %[rt],0x0250+" STR(index)                \
++      :                                               \
++      : [rt] "d" (value));                            \
++} while (0)
++
++/*
++ * The index can be 0-7.
++ */
++#define read_octeon_64bit_hash_sha512(index)          \
++({                                                    \
++      u64 __value;                                    \
++                                                      \
++      __asm__ __volatile__ (                          \
++      "dmfc2 %[rt],0x0250+" STR(index)                \
++      : [rt] "=d" (__value)                           \
++      : );                                            \
++                                                      \
++      __value;                                        \
++})
++
++/*
++ * The index can be 0-14.
++ */
++#define write_octeon_64bit_block_sha512(value, index) \
++do {                                                  \
++      __asm__ __volatile__ (                          \
++      "dmtc2 %[rt],0x0240+" STR(index)                \
++      :                                               \
++      : [rt] "d" (value));                            \
++} while (0)
++
++/*
++ * The value is the final block word (64-bit).
++ */
++#define octeon_sha512_start(value)                    \
++do {                                                  \
++      __asm__ __volatile__ (                          \
++      "dmtc2 %[rt],0x424f"                            \
++      :                                               \
 +      : [rt] "d" (value));                            \
 +} while (0)
 +
 +/*
 + * The value is the final block dword (64-bit).
 + */
 +#define octeon_sha1_start(value)                      \
 +do {                                                  \
 +      __asm__ __volatile__ (                          \
 +      "dmtc2 %[rt],0x4057"                            \
 +      :                                               \
 +      : [rt] "d" (value));                            \
 +} while (0)
 +
 +/*
 + * The value is the final block dword (64-bit).
 + */
 +#define octeon_sha256_start(value)                    \
 +do {                                                  \
 +      __asm__ __volatile__ (                          \
 +      "dmtc2 %[rt],0x404f"                            \
 +      :                                               \
 +      : [rt] "d" (value));                            \
  } while (0)
  
  /*

diff --cc arch/mips/include/asm/elf.h
Simple merge

diff --cc arch/mips/include/asm/thread_info.h
Simple merge

diff --cc arch/mips/kernel/traps.c
Simple merge

diff --cc arch/mips/lasat/sysctl.c
Simple merge

diff --cc arch/mips/pci/pci.c
index 8bb13a4,0e3f437..b8a0bf5
--- 1/arch/mips/pci/pci.c
--- 2/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@@ -91,9 -91,15 +91,12 @@@ static void pcibios_scanbus(struct pci_
  
        pci_add_resource_offset(&resources,
                                hose->mem_resource, hose->mem_offset);
-       pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
+       pci_add_resource_offset(&resources,
+                               hose->io_resource, hose->io_offset);
+       pci_add_resource_offset(&resources,
+                               hose->busn_resource, hose->busn_offset);
        bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                &resources);
 -      if (!bus)
 -              pci_free_resource_list(&resources);
 -
        hose->bus = bus;
  
        need_domain_info = need_domain_info || hose->index;

diff --cc arch/mips/sgi-ip32/ip32-platform.c
Simple merge

diff --cc drivers/clocksource/Kconfig
Simple merge

diff --cc drivers/irqchip/Kconfig
Simple merge

diff --cc drivers/irqchip/Makefile
index 552a740,89e4561..dda4927
--- 1/drivers/irqchip/Makefile
--- 2/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@@ -39,7 -37,7 +39,8 @@@ obj-$(CONFIG_TB10X_IRQC)              += irq-tb10x.
  obj-$(CONFIG_XTENSA)                  += irq-xtensa-pic.o
  obj-$(CONFIG_XTENSA_MX)                       += irq-xtensa-mx.o
  obj-$(CONFIG_IRQ_CROSSBAR)            += irq-crossbar.o
 +obj-$(CONFIG_SOC_VF610)                       += irq-vf610-mscm-ir.o
+ obj-$(CONFIG_BCM7038_L1_IRQ)          += irq-bcm7038-l1.o
  obj-$(CONFIG_BCM7120_L2_IRQ)          += irq-bcm7120-l2.o
  obj-$(CONFIG_BRCMSTB_L2_IRQ)          += irq-brcmstb-l2.o
  obj-$(CONFIG_KEYSTONE_IRQ)            += irq-keystone.o

diff --cc drivers/net/ethernet/broadcom/bgmac.c
index 5cb93d1,be059df..de77d3a
--- 1/drivers/net/ethernet/broadcom/bgmac.c
--- 2/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@@ -14,10 -14,9 +14,10 @@@
  #include <linux/etherdevice.h>
  #include <linux/mii.h>
  #include <linux/phy.h>
 +#include <linux/phy_fixed.h>
  #include <linux/interrupt.h>
  #include <linux/dma-mapping.h>
- #include <bcm47xx_nvram.h>
+ #include <linux/bcm47xx_nvram.h>
  
  static const struct bcma_device_id bgmac_bcma_tbl[] = {
        BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),

diff --cc drivers/staging/octeon/ethernet.c
Simple merge