riscv:dts: revise compatible value for PCIE/CPUfreq/idle/PMIC
authorZiv.Xu <Ziv.Xu@starfivetech.com>
Mon, 5 Sep 2022 05:19:06 +0000 (13:19 +0800)
committerZiv.Xu <Ziv.Xu@starfivetech.com>
Mon, 5 Sep 2022 06:35:42 +0000 (14:35 +0800)
revise compatible values for PCIE/CPUfreq/idle/PMIC

Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110-evb.dtsi
arch/riscv/boot/dts/starfive/jh7110.dtsi

index 58019b5..06e0de8 100644 (file)
@@ -8,8 +8,8 @@
 #include "jh7110-common.dtsi"
 
 &i2c5 {
-       pmic: stf7110_evb_reg@50 {
-               compatible = "stf,jh7110-evb-regulator";
+       pmic: jh7110_evb_reg@50 {
+               compatible = "starfive,jh7110-evb-regulator";
                reg = <0x50>;
 
                regulators {
index fc25056..729a4f1 100755 (executable)
 
     idle-states {
         CPU_RET_0_0: cpu-retentive-0-0 {
-            compatible = "riscv,idle-state";
+            compatible = "starfive,jh7110-idle-state";
             riscv,sbi-suspend-param = <0x10000000>;
             entry-latency-us = <20>;
             exit-latency-us = <40>;
         };
 
         CPU_NONRET_0_0: cpu-nonretentive-0-0 {
-            compatible = "riscv,idle-state";
+            compatible = "starfive,jh7110-idle-state";
             riscv,sbi-suspend-param = <0x90000000>;
             entry-latency-us = <250>;
             exit-latency-us = <500>;
         };
 
         CLUSTER_RET_0: cluster-retentive-0 {
-            compatible = "riscv,idle-state";
+            compatible = "starfive,jh7110-idle-state";
             riscv,sbi-suspend-param = <0x11000000>;
             local-timer-stop;
             entry-latency-us = <50>;
         };
 
         CLUSTER_NONRET_0: cluster-nonretentive-0 {
-            compatible = "riscv,idle-state";
+            compatible = "starfive,jh7110-idle-state";
             riscv,sbi-suspend-param = <0x91000000>;
             local-timer-stop;
             entry-latency-us = <600>;
                };
 
                pcie0: pcie@2B000000 {
-                       compatible = "plda,pci-xpressrich3-axi";
+                       compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
                        #address-cells = <3>;
                        #size-cells = <2>;
                        #interrupt-cells = <1>;
                };
 
                pcie1: pcie@2C000000 {
-                       compatible = "plda,pci-xpressrich3-axi";
+                       compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
                        #address-cells = <3>;
                        #size-cells = <2>;
                        #interrupt-cells = <1>;
                        };
                };
 
-               stf_cpufreq: starfive,stf-cpufreq {
-                       compatible = "starfive,stf-cpufreq";
+               starfive_cpufreq: starfive,jh7110-cpufreq {
+                       compatible = "starfive,jh7110-cpufreq";
                        clocks = <&clkgen JH7110_PLL0_OUT>,
                                         <&clkgen JH7110_CPU_ROOT>,
                                         <&osc>;