UNSPEC_PEXT
;; For AVX512F support
- UNSPEC_KMOV
+ UNSPEC_KMASKOP
UNSPEC_BNDMK
UNSPEC_BNDMK_ADDR
]
(const_string "SI")))])
-(define_insn "kmovw"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=k,k")
- (unspec:HI
- [(match_operand:HI 1 "nonimmediate_operand" "r,km")]
- UNSPEC_KMOV))]
- "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- kmovw\t{%k1, %0|%0, %k1}
- kmovw\t{%1, %0|%0, %1}";
- [(set_attr "type" "mskmov")
- (set_attr "prefix" "vex")
- (set_attr "mode" "HI")])
+(define_expand "kmovw"
+ [(set (match_operand:HI 0 "nonimmediate_operand")
+ (match_operand:HI 1 "nonimmediate_operand"))]
+ "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k ,r,m")
operands[3] = gen_lowpart (QImode, operands[3]);
})
-(define_split
- [(set (match_operand:SWI1248x 0 "mask_reg_operand")
- (any_logic:SWI1248x (match_operand:SWI1248x 1 "mask_reg_operand")
- (match_operand:SWI1248x 2 "mask_reg_operand")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_AVX512F && reload_completed"
- [(set (match_dup 0)
- (any_logic:SWI1248x (match_dup 1)
- (match_dup 2)))])
-
-(define_insn "*k<logic><mode>"
- [(set (match_operand:SWI1248_AVX512BW 0 "mask_reg_operand" "=k")
+(define_insn "k<code><mode>"
+ [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
(any_logic:SWI1248_AVX512BW
- (match_operand:SWI1248_AVX512BW 1 "mask_reg_operand" "k")
- (match_operand:SWI1248_AVX512BW 2 "mask_reg_operand" "k")))]
+ (match_operand:SWI1248_AVX512BW 1 "register_operand" "k")
+ (match_operand:SWI1248_AVX512BW 2 "register_operand" "k")))
+ (unspec [(const_int 0)] UNSPEC_KMASKOP)]
"TARGET_AVX512F"
- {
- if (get_attr_mode (insn) == MODE_HI)
- return "k<logic>w\t{%2, %1, %0|%0, %1, %2}";
- else
- return "k<logic><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
- }
+{
+ if (get_attr_mode (insn) == MODE_HI)
+ return "k<logic>w\t{%2, %1, %0|%0, %1, %2}";
+ else
+ return "k<logic><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
+}
[(set_attr "type" "msklog")
(set_attr "prefix" "vex")
(set (attr "mode")
})
(define_insn "*anddi_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r,!k")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
(and:DI
- (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm,k")
- (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L,k")))
+ (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
+ (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
{
case TYPE_IMOVX:
return "#";
- case TYPE_MSKLOG:
- return "kandq\t{%2, %1, %0|%0, %1, %2}";
-
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (get_attr_mode (insn) == MODE_SI)
return "and{q}\t{%2, %0|%0, %2}";
}
}
- [(set_attr "type" "alu,alu,alu,imovx,msklog")
- (set_attr "length_immediate" "*,*,*,0,0")
+ [(set_attr "type" "alu,alu,alu,imovx")
+ (set_attr "length_immediate" "*,*,*,0")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI,DI,DI,SI,DI")])
+ (set_attr "mode" "SI,DI,DI,SI")])
;; Turn *anddi_1 into *andsi_1_zext if possible.
(define_split
(set_attr "mode" "SI")])
(define_insn "*andsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm,k")
- (match_operand:SI 2 "x86_64_general_operand" "re,rm,L,k")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
+ (match_operand:SI 2 "x86_64_general_operand" "re,rm,L")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, SImode, operands)"
{
case TYPE_IMOVX:
return "#";
- case TYPE_MSKLOG:
- return "kandd\t{%2, %1, %0|%0, %1, %2}";
-
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "and{l}\t{%2, %0|%0, %2}";
}
}
- [(set_attr "type" "alu,alu,imovx,msklog")
+ [(set_attr "type" "alu,alu,imovx")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
- (set_attr "length_immediate" "*,*,0,0")
+ (set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
(define_insn "*andhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm,k")
- (match_operand:HI 2 "general_operand" "rn,rm,L,k")))
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya")
+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
+ (match_operand:HI 2 "general_operand" "rn,rm,L")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, HImode, operands)"
{
case TYPE_IMOVX:
return "#";
- case TYPE_MSKLOG:
- return "kandw\t{%2, %1, %0|%0, %1, %2}";
-
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "and{w}\t{%2, %0|%0, %2}";
}
}
- [(set_attr "type" "alu,alu,imovx,msklog")
- (set_attr "length_immediate" "*,*,0,*")
+ [(set_attr "type" "alu,alu,imovx")
+ (set_attr "length_immediate" "*,*,0")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_operand"))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "HI,HI,SI,HI")])
+ (set_attr "mode" "HI,HI,SI")])
(define_insn "*andqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,!k")
- (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn,k")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, QImode, operands)"
{
return "and{b}\t{%2, %0|%0, %2}";
case 2:
return "and{l}\t{%k2, %k0|%k0, %k2}";
- case 3:
- if (get_attr_mode (insn) == MODE_HI)
- return "kandw\t{%2, %1, %0|%0, %1, %2}";
- else
- return "kandb\t{%2, %1, %0|%0, %1, %2}";
default:
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,alu,msklog")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "2")
- (const_string "SI")
- (and (eq_attr "alternative" "3")
- (not (match_test "TARGET_AVX512DQ")))
- (const_string "HI")]
- (const_string "QI")))
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI,QI,SI")
;; Potential partial reg stall on alternative 2.
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "2")
})
(define_insn "kandn<mode>"
- [(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k")
- (and:SWI12
- (not:SWI12
- (match_operand:SWI12 1 "register_operand" "r,0,k"))
- (match_operand:SWI12 2 "register_operand" "r,r,k")))
- (clobber (reg:CC FLAGS_REG))]
+ [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
+ (and:SWI1248_AVX512BW
+ (not:SWI1248_AVX512BW
+ (match_operand:SWI1248_AVX512BW 1 "register_operand" "k"))
+ (match_operand:SWI1248_AVX512BW 2 "register_operand" "k")))
+ (unspec [(const_int 0)] UNSPEC_KMASKOP)]
"TARGET_AVX512F"
{
- switch (which_alternative)
- {
- case 0:
- return "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}";
- case 1:
- return "#";
- case 2:
- if (get_attr_mode (insn) == MODE_HI)
- return "kandnw\t{%2, %1, %0|%0, %1, %2}";
- else
- return "kandn<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
- default:
- gcc_unreachable ();
- }
+ if (get_attr_mode (insn) == MODE_HI)
+ return "kandnw\t{%2, %1, %0|%0, %1, %2}";
+ else
+ return "kandn<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
}
- [(set_attr "isa" "bmi,*,avx512f")
- (set_attr "type" "bitmanip,*,msklog")
- (set_attr "prefix" "*,*,vex")
- (set_attr "btver2_decode" "direct,*,*")
+ [(set_attr "type" "msklog")
+ (set_attr "prefix" "vex")
(set (attr "mode")
- (cond [(and (eq_attr "alternative" "2")
- (and (match_test "<MODE>mode == QImode")
- (not (match_test "TARGET_AVX512DQ"))))
- (const_string "HI")
+ (cond [(and (match_test "<MODE>mode == QImode")
+ (not (match_test "TARGET_AVX512DQ")))
+ (const_string "HI")
]
(const_string "<MODE>")))])
-(define_split
- [(set (match_operand:SWI12 0 "general_reg_operand")
- (and:SWI12
- (not:SWI12
- (match_dup 0))
- (match_operand:SWI12 1 "general_reg_operand")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_AVX512F && !TARGET_BMI && reload_completed"
- [(set (match_dup 0)
- (not:SWI12 (match_dup 0)))
- (parallel [(set (match_dup 0)
- (and:SWI12 (match_dup 0)
- (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
-
(define_insn_and_split "*andndi3_doubleword"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI
(clobber (reg:CC FLAGS_REG))])]
"split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
-(define_insn "*bmi_andn_<mode>"
+(define_insn "*andn<mode>_1"
[(set (match_operand:SWI48 0 "register_operand" "=r,r")
(and:SWI48
(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
(set_attr "btver2_decode" "direct, double")
(set_attr "mode" "<MODE>")])
+(define_insn "*andn<mode>_1"
+ [(set (match_operand:SWI12 0 "register_operand" "=r")
+ (and:SWI12
+ (not:SWI12 (match_operand:SWI12 1 "register_operand" "r"))
+ (match_operand:SWI12 2 "register_operand" "r")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_BMI"
+ "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}"
+ [(set_attr "type" "bitmanip")
+ (set_attr "btver2_decode" "direct")
+ (set_attr "mode" "SI")])
+
(define_insn "*bmi_andn_<mode>_ccno"
[(set (reg FLAGS_REG)
(compare
})
(define_insn "*<code><mode>_1"
- [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,k")
- (any_or:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,k")
- (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,k")))
+ [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
+ (any_or:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "@
- <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
- <logic>{<imodesuffix>}\t{%2, %0|%0, %2}
- k<logic><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "alu,alu,msklog")
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ [(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
;; See comment for addsi_1_zext why we do use nonimmediate_operand
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*<code>hi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k")
- (any_or:HI
- (match_operand:HI 1 "nonimmediate_operand" "%0,0,k")
- (match_operand:HI 2 "general_operand" "rmn,rn,k")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (<CODE>, HImode, operands)"
- "@
- <logic>{w}\t{%2, %0|%0, %2}
- <logic>{w}\t{%2, %0|%0, %2}
- k<logic>w\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "alu,alu,msklog")
- (set_attr "mode" "HI")])
-
(define_insn "*<code>qi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r,!k")
- (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k")
- (match_operand:QI 2 "general_operand" "qmn,qn,rn,k")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
+ (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, QImode, operands)"
"@
<logic>{b}\t{%2, %0|%0, %2}
<logic>{b}\t{%2, %0|%0, %2}
- <logic>{l}\t{%k2, %k0|%k0, %k2}
- k<logic>w\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "alu,alu,alu,msklog")
- (set_attr "mode" "QI,QI,SI,HI")
+ <logic>{l}\t{%k2, %k0|%k0, %k2}"
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI,QI,SI")
;; Potential partial reg stall on alternative 2.
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "2")
(set_attr "mode" "QI")])
(define_insn "kxnor<mode>"
- [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=r,!k")
+ [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
(not:SWI1248_AVX512BW
(xor:SWI1248_AVX512BW
- (match_operand:SWI1248_AVX512BW 1 "register_operand" "0,k")
- (match_operand:SWI1248_AVX512BW 2 "register_operand" "r,k"))))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:SWI1248_AVX512BW 1 "register_operand" "k")
+ (match_operand:SWI1248_AVX512BW 2 "register_operand" "k"))))
+ (unspec [(const_int 0)] UNSPEC_KMASKOP)]
"TARGET_AVX512F"
{
- if (which_alternative == 0)
- return "#";
-
if (get_attr_mode (insn) == MODE_HI)
return "kxnorw\t{%2, %1, %0|%0, %1, %2}";
else
return "kxnor<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
}
- [(set_attr "type" "*,msklog")
- (set_attr "prefix" "*,vex")
+ [(set_attr "type" "msklog")
+ (set_attr "prefix" "vex")
(set (attr "mode")
- (cond [(and (eq_attr "alternative" "1")
- (and (match_test "<MODE>mode == QImode")
- (not (match_test "TARGET_AVX512DQ"))))
+ (cond [(and (match_test "<MODE>mode == QImode")
+ (not (match_test "TARGET_AVX512DQ")))
(const_string "HI")
]
(const_string "<MODE>")))])
-(define_split
- [(set (match_operand:SWI1248x 0 "general_reg_operand")
- (not:SWI1248x
- (xor:SWI1248x
- (match_dup 0)
- (match_operand:SWI1248x 1 "general_reg_operand"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_AVX512F && reload_completed"
- [(parallel [(set (match_dup 0)
- (xor:SWI1248x (match_dup 0)
- (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])
- (set (match_dup 0)
- (not:SWI1248x (match_dup 0)))])
-
;;There are kortrest[bdq] but no intrinsics for them.
;;We probably don't need to implement them.
(define_insn "kortestzhi"
\f
;; One complement instructions
+(define_insn "knot<mode>"
+ [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
+ (not:SWI1248_AVX512BW
+ (match_operand:SWI1248_AVX512BW 1 "register_operand" "k")))
+ (unspec [(const_int 0)] UNSPEC_KMASKOP)]
+ "TARGET_AVX512F"
+{
+ if (get_attr_mode (insn) == MODE_HI)
+ return "knotw\t{%1, %0|%0, %1}";
+ else
+ return "knot<mskmodesuffix>\t{%1, %0|%0, %1}";
+}
+ [(set_attr "type" "msklog")
+ (set_attr "prefix" "vex")
+ (set (attr "mode")
+ (cond [(and (match_test "<MODE>mode == QImode")
+ (not (match_test "TARGET_AVX512DQ")))
+ (const_string "HI")
+ ]
+ (const_string "<MODE>")))])
+
(define_expand "one_cmpl<mode>2"
[(set (match_operand:SWIM 0 "nonimmediate_operand")
(not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))]
"ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
(define_insn "*one_cmpl<mode>2_1"
- [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,k")
- (not:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,k")))]
+ [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm")
+ (not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0")))]
"ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
- "@
- not{<imodesuffix>}\t%0
- knot<mskmodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "isa" "*,avx512bw")
- (set_attr "type" "negnot,msklog")
- (set_attr "prefix" "*,vex")
+ "not{<imodesuffix>}\t%0"
+ [(set_attr "type" "negnot")
(set_attr "mode" "<MODE>")])
;; ??? Currently never generated - xor is used instead.
[(set_attr "type" "negnot")
(set_attr "mode" "SI")])
-(define_insn "*one_cmplhi2_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,!k")
- (not:HI (match_operand:HI 1 "nonimmediate_operand" "0,k")))]
- "ix86_unary_operator_ok (NOT, HImode, operands)"
- "@
- not{w}\t%0
- knotw\t{%1, %0|%0, %1}"
- [(set_attr "isa" "*,avx512f")
- (set_attr "type" "negnot,msklog")
- (set_attr "prefix" "*,vex")
- (set_attr "mode" "HI")])
-
(define_insn "*one_cmplqi2_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,!k")
- (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,k")))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
+ (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
"ix86_unary_operator_ok (NOT, QImode, operands)"
-{
- switch (which_alternative)
- {
- case 0:
- return "not{b}\t%0";
- case 1:
- return "not{l}\t%k0";
- case 2:
- if (get_attr_mode (insn) == MODE_HI)
- return "knotw\t{%1, %0|%0, %1}";
- else
- return "knotb\t{%1, %0|%0, %1}";
- default:
- gcc_unreachable ();
- }
-}
- [(set_attr "isa" "*,*,avx512f")
- (set_attr "type" "negnot,negnot,msklog")
- (set_attr "prefix" "*,*,vex")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "1")
- (const_string "SI")
- (and (eq_attr "alternative" "2")
- (not (match_test "TARGET_AVX512DQ")))
- (const_string "HI")]
- (const_string "QI")))
+ "@
+ not{b}\t%0
+ not{l}\t%k0"
+ [(set_attr "type" "negnot")
+ (set_attr "mode" "QI,SI")
;; Potential partial reg stall on alternative 1.
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "1")
;; shift pair, instead using moves and sign extension for counts greater
;; than 31.
-(define_insn "*<mshift><mode>3"
+(define_insn "*k<code><mode>"
[(set (match_operand:SWI1248_AVX512BWDQ 0 "register_operand" "=k")
- (any_lshift:SWI1248_AVX512BWDQ (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k")
- (match_operand:QI 2 "immediate_operand" "i")))]
+ (any_lshift:SWI1248_AVX512BWDQ
+ (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k")
+ (match_operand:QI 2 "immediate_operand" "n")))
+ (unspec [(const_int 0)] UNSPEC_KMASKOP)]
"TARGET_AVX512F"
"k<mshift><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "msklog")
- (set_attr "prefix" "vex")])
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
(define_expand "ashl<mode>3"
[(set (match_operand:SDWIM 0 "<shift_operand>")
projects / platform / upstream / gcc.git / commitdiff