[AMDGPU][MC][GFX8+] Correct v_cndmask modifiers

Correct v_cndmask_b32 to support abs/neg modifiers in dpp/sdwa/e64 variants.
Correct v_cndmask_b16 for proper disassembly of abs/neg modifiers in e64_dpp variants.

Differential Revision: https://reviews.llvm.org/D135900

diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 15069a0..c1448ae 100644 (file)
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -769,7 +769,6 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
@@ -781,7 +780,6 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
-  case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
@@ -844,6 +842,20 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
   if (NegMnemo) {
     O << ')';
   }
+
+  // Print default vcc/vcc_lo operand of VOP2b.
+  switch (MI->getOpcode()) {
+  default:
+    break;
+
+  case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
+  case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
+  case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
+    if ((int)OpNo + 1 ==
+        AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
+      printDefaultVccOperand(OpNo == 0, STI, O);
+    break;
+  }
 }
 
 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
@@ -865,7 +877,6 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
   switch (MI->getOpcode()) {
   default: break;
 
-  case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:

diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 98bc164..a04eb98 100644 (file)
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -581,7 +581,7 @@ class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT, /*EnableF32SrcMods=*
   let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
   let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
   let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
-  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
+  let AsmDPP = "$vdst, $src0_modifiers, $src1_modifiers, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
   let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
   let AsmDPP16 = AsmDPP#"$fi";
   let AsmVOP3DPPBase = Asm64;
@@ -593,23 +593,30 @@ class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT, /*EnableF32SrcMods=*
   // implicit VCC use.
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
 
-  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
-                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
+  let HasSrc0IntMods = 0;
+  let HasSrc1IntMods = 0;
+  let HasSrc0FloatMods = 1;
+  let HasSrc1FloatMods = 1;
+  let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,
+                     FP32SDWAInputMods:$src1_modifiers, Src1SDWA:$src1,
                      clampmod:$clamp,
                      dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel, src1_sel:$src1_sel);
 
   let InsDPP = (ins DstRCDPP:$old,
-                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
-                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
+                    FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
+                    FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
   let InsDPP16 = !con(InsDPP, (ins FI:$fi));
   let InsDPP8 = (ins DstRCDPP:$old,
-                     Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
-                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
+                     FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
+                     FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
                      dpp8:$dpp8, FI:$fi);
 
+  let Src0ModVOP3DPP = FPVRegInputMods;
+  let Src1ModVOP3DPP = FPVRegInputMods;
+
   let HasExt = 1;
   let HasExtDPP = 1;
   let HasExt32BitDPP = 1;

diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
index 8519e91..1393c9e 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
@@ -99,6 +99,34 @@ v_cndmask_b32_e64 v5, v1, v2, vcc
 // W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// W64: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// W64: encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_e32 v5, v1, v2, vcc_lo
 // W32: encoding: [0x01,0x05,0x0a,0x02]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -191,6 +219,42 @@ v_cndmask_b32_e64 v5, v1, v2, vcc_lo
 // W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc_lo
+// W32: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc_lo
+// W32: encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand
+
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_add_f32_e32 v5, v1, v2
 // GFX10: encoding: [0x01,0x05,0x0a,0x06]
 

diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index cc5fd58..3fee1c0 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -1344,3 +1344,11 @@ ds_swizzle_b32 v8, v2 offset:0x10000
 // CHECK: error: expected a 16-bit offset
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000
 // CHECK-NEXT:{{^}}                             ^
+
+//==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                           ^

diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index 6e9e253..6755a2a 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -377,6 +377,18 @@ v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ct
 // W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32 v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // W32: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -437,6 +449,18 @@ v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 boun
 // W64: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 // GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 

diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
index 143fc65..804e1c2 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
@@ -4968,6 +4968,15 @@ v_cndmask_b32_e64 v5, v1, v2, tma
 v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd2,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd2,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd2,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
 

diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
index 1ee5623..d3540ba 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
@@ -3954,8 +3954,11 @@ v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
 
-v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+v_cndmask_b32_sdwa v5, |v1|, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x06]
+
+v_cndmask_b32_sdwa v5, -v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
@@ -3978,8 +3981,11 @@ v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
 
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+v_cndmask_b32_sdwa v5, v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x26]
+
+v_cndmask_b32_sdwa v5, v1, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x16]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
@@ -4065,6 +4071,15 @@ v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x98,0x00]
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x68,0x00]
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf8,0x00]
+
 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
 

diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
index 429133b..d4c31f1 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
@@ -6066,6 +6066,15 @@ v_cndmask_b32_e64 v5, v1, v2, tma
 v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 

diff --git a/llvm/test/MC/AMDGPU/gfx8_err_pos.s b/llvm/test/MC/AMDGPU/gfx8_err_pos.s
index 382245f..3f21398 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx8_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx8_err_pos.s
@@ -41,3 +41,11 @@ image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK: error: image data size does not match dmask and tfe
 // CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK-NEXT:{{^}}^
+
+//==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                           ^

diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
index c7a5f94..f5c6066 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
@@ -3657,8 +3657,11 @@ v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
 
-v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+v_cndmask_b32_sdwa v5, -v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x06]
+
+v_cndmask_b32_sdwa v5, |v1|, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
@@ -3681,8 +3684,11 @@ v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
 
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+v_cndmask_b32_sdwa v5, v1, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x16]
+
+v_cndmask_b32_sdwa v5, v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x26]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
@@ -3768,6 +3774,15 @@ v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x98,0x00]
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x68,0x00]
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf8,0x00]
+
 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
 

diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
index bfed5e3..8781a01 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
@@ -5589,6 +5589,15 @@ v_cndmask_b32_e64 v5, v1, v2, vcc
 v_cndmask_b32_e64 v5, v1, v2, ttmp[14:15]
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 

diff --git a/llvm/test/MC/AMDGPU/gfx9_err_pos.s b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
index d91bd0f..b9ad41e 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx9_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
@@ -221,6 +221,14 @@ tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORM
 // CHECK-NEXT:{{^}}                                                            ^
 
 //==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                       ^
+
+//==============================================================================
 // out of range dfmt
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0

diff --git a/llvm/test/MC/AMDGPU/vop_sdwa.s b/llvm/test/MC/AMDGPU/vop_sdwa.s
index 5bd6496..026ada8 100644 (file)
--- a/llvm/test/MC/AMDGPU/vop_sdwa.s
+++ b/llvm/test/MC/AMDGPU/vop_sdwa.s
@@ -593,8 +593,12 @@ v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel
 v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 
 // NOSICI: error: not a valid operand.
-// GFX89:  v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX89:  v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26]
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICI: error: not a valid operand.
+// GFX89:  v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16]
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 
 v_cndmask_b32_sdwa v5, vcc_lo, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
 // NOSICI: error: not a valid operand
@@ -1089,6 +1093,14 @@ v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WO
 // GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00]
 v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0
 
+// NOSICI: error: not a valid operand.
+// NOGFX89: error: not a valid operand.
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICI: error: not a valid operand.
+// NOGFX89: error: not a valid operand.
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
 //===----------------------------------------------------------------------===//
 // Validate register size checks (bug 37943)
 //===----------------------------------------------------------------------===//

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
index 164585b..998ef19 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
@@ -2464,3 +2464,15 @@
 
 # GFX10: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00
+
+# W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+# W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff
+
+# W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+# W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff
+
+# W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+# W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
index 152606a..4746404 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
@@ -3709,3 +3709,15 @@
 
 # GFX10: v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06
+
+# W32: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15]
+# W64: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15
+
+# W32: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25]
+# W64: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25
+
+# W32: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35]
+# W64: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
index a9d761b..66ce6b8 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
@@ -2454,6 +2454,18 @@
 # W64: v_cndmask_b32_e64 v5, v255, v2, s[6:7]  ; encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
 0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00
 
+# W32: v_cndmask_b32_e64 v5, -v1, |v2|, vcc_lo ; encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+# W64: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21
+
+# W32: v_cndmask_b32_e64 v5, |v1|, -v2, vcc_lo ; encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+# W64: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41
+
+# W32: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc_lo ; encoding: [0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61]
+# W64: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61
+
 # GFX10: v_cos_f16_e64 v255, v1                  ; encoding: [0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
 0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00
 

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
index 94bb71f..7f80bf6 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
@@ -323,6 +323,18 @@
 # W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30
 
+# W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+# W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff
+
+# W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+# W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff
+
+# W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+# W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff
+
 # GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff
 

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
index 5f55d30..2f9f85f 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
@@ -1129,6 +1129,12 @@
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
 0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
 
+# GFX11: v_cndmask_b16_e64_dpp v5, -v1, |v2|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x09,0x30]
+0x05,0x02,0x5d,0xd6,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x09,0x30
+
+# GFX11: v_cndmask_b16_e64_dpp v5, |v1|, -v2, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x09,0x30]
+0x05,0x01,0x5d,0xd6,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x09,0x30
+
 # GFX11: v_cndmask_b16_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
 0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
 
@@ -1187,6 +1193,12 @@
 # GFX11: v_cndmask_b32_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
 0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
 
+# GFX11: v_cndmask_b32_e64_dpp v5, -v1, |v2|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x05,0x02,0x01,0xd5,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x0d,0x30]
+0x05,0x02,0x01,0xd5,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x0d,0x30
+
+# GFX11: v_cndmask_b32_e64_dpp v5, |v1|, -v2, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x05,0x01,0x01,0xd5,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x0d,0x30]
+0x05,0x01,0x01,0xd5,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x0d,0x30
+
 # GFX11: v_cos_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
 

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
index e883b56..525940b 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
@@ -451,6 +451,12 @@
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
 
+# GFX11: v_cndmask_b16_e64_dpp v5, -v1, |v2|, null dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x05,0x02,0x5d,0xd6,0xe9,0x04,0xf2,0x21,0x01,0x00,0x00,0x00]
+0x05,0x02,0x5d,0xd6,0xe9,0x04,0xf2,0x21,0x01,0x00,0x00,0x00
+
+# GFX11: v_cndmask_b16_e64_dpp v5, |v1|, -v2, null dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x05,0x01,0x5d,0xd6,0xe9,0x04,0xf2,0x41,0x01,0x00,0x00,0x00]
+0x05,0x01,0x5d,0xd6,0xe9,0x04,0xf2,0x41,0x01,0x00,0x00,0x00
+
 # GFX11: v_cndmask_b16_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
 0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
 
@@ -473,6 +479,12 @@
 # GFX11: v_cndmask_b32_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
 0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
 
+# GFX11: v_cndmask_b32_e64_dpp v5, -v1, |v2|, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x05,0x02,0x01,0xd5,0xea,0x04,0xf2,0x21,0x01,0x00,0x00,0x00]
+0x05,0x02,0x01,0xd5,0xea,0x04,0xf2,0x21,0x01,0x00,0x00,0x00
+
+# GFX11: v_cndmask_b32_e64_dpp v5, |v1|, -v2, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x05,0x01,0x01,0xd5,0xea,0x04,0xf2,0x41,0x01,0x00,0x00,0x00]
+0x05,0x01,0x01,0xd5,0xea,0x04,0xf2,0x41,0x01,0x00,0x00,0x00
+
 # GFX11: v_cos_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
 

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
index 892c27b..7233bf8 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
@@ -3899,3 +3899,12 @@
 
 # CHECK: v_cndmask_b32_dpp v255, v255, v255, vcc row_ror:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xfe,0xff,0x01,0xff,0x2f,0x09,0x30]
 0xfa,0xfe,0xff,0x01,0xff,0x2f,0x09,0x30
+
+# CHECK: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
index 12d7852..f3f25f4 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
@@ -3822,5 +3822,11 @@
 # CHECK: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3 ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x04,0x05,0x03]
 0xf9,0x04,0x0a,0x00,0x01,0x04,0x05,0x03
 
-# CHECK: v_cndmask_b32_sdwa v255, sext(v255), sext(v255), vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x0e,0x0d]
-0xf9,0xfe,0xff,0x01,0xff,0x0d,0x0e,0x0d
+# CHECK: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x26,0x15]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x26,0x15
+
+# CHECK: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x16,0x25]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x16,0x25
+
+# CHECK: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x36,0x35]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x36,0x35

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
index ae031c9..2b07d62 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
@@ -5211,6 +5211,15 @@
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11] ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01
 
+# CHECK: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21
+
+# CHECK: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41
+
+# CHECK: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61
+
 # CHECK: v_add_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00
 

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
index 54fbd17..94b9850 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
@@ -399,8 +399,14 @@
 # GFX9: v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06
 
-# GFX9: v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
-0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e
+# GFX9: v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26
+
+# GFX9: v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16
+
+# GFX9: v_cndmask_b32_sdwa v5, -|v1|, -|v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x36,0x36]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x36,0x36
 
 #-----------------------------------------------------------------------------#
 # VOPC

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
index 4af126d..352f15f 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
@@ -4085,3 +4085,12 @@
 
 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00
+
+# CHECK: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
index b570683..af8e0df 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
@@ -4248,6 +4248,15 @@
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, vcc       ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01
 
+# CHECK: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21
+
+# CHECK: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41
+
+# CHECK: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61
+
 # CHECK: v_add_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00