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RISC-V: Add SSTC extension CSR details
author
Atish Patra
<atishp@rivosinc.com>
Fri, 22 Jul 2022 16:50:44 +0000
(09:50 -0700)
committer
Palmer Dabbelt
<palmer@rivosinc.com>
Thu, 11 Aug 2022 21:36:06 +0000
(14:36 -0700)
This patch just introduces the required CSR fields related to the
SSTC extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link:
https://lore.kernel.org/r/20220722165047.519994-2-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/csr.h
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diff --git
a/arch/riscv/include/asm/csr.h
b/arch/riscv/include/asm/csr.h
index 6d85655e7edf26aabfe4b8345a3d95851fd8a87b..34f4eaf326c45e9078061fd4a6853a23c91716cd 100644
(file)
--- a/
arch/riscv/include/asm/csr.h
+++ b/
arch/riscv/include/asm/csr.h
@@
-235,6
+235,9
@@
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_STIMECMP 0x14D
+#define CSR_STIMECMPH 0x15D
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@
-244,6
+247,8
@@
#define CSR_VSTVAL 0x243
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602