+2017-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use
+ HAS_CPU_FEATURE to check for SSE.
+ * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
+ * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise.
+ * sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise.
+ * sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise.
+ * sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise.
+ * sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise.
+ * sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise.
+ * sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise.
+ * sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise.
+ * sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise.
+ * sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise.
+ * sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise.
+ * sysdeps/i386/setfpucw.c (__setfpucw): Likewise.
+ * sysdeps/x86/cpu-features.h (bit_cpu_SSE): New.
+ (index_cpu_SSE): Likewise.
+ (reg_SSE): Likewise.
+
2017-04-07 Paul Eggert <eggert@cs.ucla.edu>
* posix/getopt1.c: Include <config.h>, not "config.h".
__asm__ ("fldenv %0" : : "m" (*&temp));
/* If the CPU supports SSE, we clear the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;
would block all exceptions. */
__asm__ ("fldenv %0" : : "m" (*envp));
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (envp->__eip));
/* Success. */
fegetmode (femode_t *modep)
{
_FPU_GETCW (modep->__control_word);
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (modep->__mxcsr));
return 0;
}
__asm__ volatile ("fnstenv %0; fnclex" : "=m" (*envp));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xwork;
__asm__ ("fldenv %0" : : "m" (temp));
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int mxcsr;
__asm__ ("stmxcsr %0" : "=m" (mxcsr));
else
cw = modep->__control_word;
_FPU_SETCW (cw);
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int mxcsr;
__asm__ ("stmxcsr %0" : "=m" (mxcsr));
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xcw;
__asm__ ("fnstsw %0" : "=m" (*&temp));
/* If the CPU supports SSE we test the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
temp = (temp | xtemp) & FE_ALL_EXCEPT;
*flagp = temp & excepts & FE_ALL_EXCEPT;
/* If the CPU supports SSE, we clear the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int sse_exc;
__asm__ ("fldenv %0" : : "m" (*&temp));
/* If the CPU supports SSE, we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;
__asm__ ("fnstsw %0" : "=a" (temp));
/* If the CPU supports SSE we test the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE, we set the MXCSR as well. */
- if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;
/* COMMON_CPUID_INDEX_1. */
#define bit_cpu_CX8 (1 << 8)
#define bit_cpu_CMOV (1 << 15)
+#define bit_cpu_SSE (1 << 25)
#define bit_cpu_SSE2 (1 << 26)
#define bit_cpu_SSSE3 (1 << 9)
#define bit_cpu_SSE4_1 (1 << 19)
# define index_cpu_CX8 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_CMOV COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
+# define index_cpu_SSE COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_SSE2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
# define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
# define index_cpu_CX8 COMMON_CPUID_INDEX_1
# define index_cpu_CMOV COMMON_CPUID_INDEX_1
+# define index_cpu_SSE COMMON_CPUID_INDEX_1
# define index_cpu_SSE2 COMMON_CPUID_INDEX_1
# define index_cpu_SSSE3 COMMON_CPUID_INDEX_1
# define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1
# define reg_CX8 edx
# define reg_CMOV edx
+# define reg_SSE edx
# define reg_SSE2 edx
# define reg_SSSE3 ecx
# define reg_SSE4_1 ecx