ARM: dts: omap5: add SHA crypto accelerator node

Add the single available SHA crypto accelerator device for OMAP5 SoC.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 0079116..5e74f44 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -305,6 +305,34 @@
                        };
                };
 
+               sham_target: target-module@4b100000 {
+                       compatible = "ti,sysc-omap3-sham", "ti,sysc";
+                       reg = <0x4b100100 0x4>,
+                             <0x4b100110 0x4>,
+                             <0x4b100114 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+                       clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4b100000 0x1000>;
+
+                       sham: sham@0 {
+                               compatible = "ti,omap4-sham";
+                               reg = <0 0x300>;
+                               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&sdma 119>;
+                               dma-names = "rx";
+                       };
+               };
+
                bandgap: bandgap@4a0021e0 {
                        reg = <0x4a0021e0 0xc
                               0x4a00232c 0xc