;; multiple instructions, patterns which emit 0 instructions, and patterns
;; which emit instruction that can go in any slot (e.g. nop).
-(define_attr "type" "unknown,A,I,M,F,B,L,S" (const_string "unknown"))
+(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd"
+ (const_string "unknown"))
+
+(define_attr "type" "unknown,A,I,M,F,B,L,S"
+ (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem") (const_string "M")
+ (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
+ (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
+ (eq_attr "itanium_class" "ialu,icmp,ilog") (const_string "A")
+ (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy,fcvtfx") (const_string "F")
+ (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
+ (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
+ (eq_attr "itanium_class" "mmmul,mmshf,mmshfi") (const_string "I")
+ (eq_attr "itanium_class" "br,scall") (const_string "B")
+ (eq_attr "itanium_class" "stop_bit") (const_string "S")
+ (eq_attr "itanium_class" "long_i") (const_string "L")]
+ (const_string "unknown")))
;; Predication. True iff this instruction can be predicated.
cmp.ne %0, p0 = r0, r0
cmp.eq %0, p0 = r0, r0
(%1) cmp.eq.unc %0, p0 = r0, r0"
- [(set_attr "type" "A")
+ [(set_attr "itanium_class" "icmp")
(set_attr "predicable" "no")])
(define_insn "movbi"
ld1%O1 %0 = %1%P1
st1%Q0 %0 = %1%P0
mov %0 = %1"
- [(set_attr "type" "A,A,unknown,unknown,I,A,M,M,A")])
+ [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
(define_split
[(set (match_operand:BI 0 "register_operand" "")
(%J2) getf.sig %0 = %1
(%J2) setf.sig %0 = %r1
(%J2) mov %0 = %1"
- [(set_attr "type" "A,A,M,M,F")
+ [(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movqi_internal_astep"
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M,F")
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movqi_internal"
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M,F")])
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
(%J2) getf.sig %0 = %1
(%J2) setf.sig %0 = %r1
(%J2) mov %0 = %1"
- [(set_attr "type" "A,A,M,M,F")
+ [(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movhi_internal_astep"
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M,F")
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
(set_attr "predicable" "no")])
(define_insn "*movhi_internal"
getf.sig %0 = %1
setf.sig %0 = %r1
mov %0 = %1"
- [(set_attr "type" "A,A,M,M,M,M,F")])
+ [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
(%J2) mov %0 = %1
(%J2) mov %0 = %1
(%J2) mov %0 = %r1"
- [(set_attr "type" "A,A,L,M,M,F,M,M")
+;; frar_m, toar_m ??? why not frar_i and toar_i
+ [(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frar_m,toar_m")
(set_attr "predicable" "no")])
(define_insn "*movsi_internal_astep"
mov %0 = %1
mov %0 = %1
mov %0 = %r1"
- [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")
+;; frar_m, toar_m ??? why not frar_i and toar_i
+ [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
(set_attr "predicable" "no")])
(define_insn "*movsi_internal"
mov %0 = %1
mov %0 = %1
mov %0 = %r1"
- [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
+;; frar_m, toar_m ??? why not frar_i and toar_i
+ [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
(define_insn ""
[(cond_exec
(match_operator 2 "predicate_operator"
- [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c")
+ [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c,c")
(const_int 0)])
(set (match_operand:DI 0 "register_operand"
- "=r,r,r, r,*f,*f, r,*b,*e, r,*d")
+ "=r,r,r, r,*f,*f, r,*b, r,*e, r,*d")
(match_operand:DI 1 "nonmemory_operand"
- "rO,J,i,*f,rO,*f,*b*e,rO,rK,*d,rK")))]
+ "rO,J,i,*f,rO,*f,*b,rO,*e,rK,*d,rK")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"*
{
\"(%J2) mov %0 = %r1\",
\"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\",
+ \"(%J2) mov %0 = %1\",
\"(%J2) mov %0 = %1\"
};
return alt[which_alternative];
}"
- [(set_attr "type" "A,A,L,M,M,F,I,I,I,M,M")
+ [(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frbr,tobr,frar_i,toar_i,frar_m,toar_m")
(set_attr "predicable" "no")])
;; This is used during early compilation to delay the decision on
(define_insn "*movdi_internal_astep"
[(set (match_operand:DI 0 "destination_operand"
- "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b,*e, r,*d, r,*c")
+ "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
(match_operand:DI 1 "move_operand"
- "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,rO,rK,*d,rK,*c,rO"))]
+ "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"*
{
\"mov %0 = %1\",
\"mov %0 = %1\",
\"mov %0 = %1\",
+ \"mov %0 = %1\",
\"mov %0 = pr\",
\"mov pr = %1, -1\"
};
return alt[which_alternative];
}"
- [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,I,M,M,I,I")
+ [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
(set_attr "predicable" "no")])
(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "destination_operand"
- "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b,*e, r,*d, r,*c")
+ "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
(match_operand:DI 1 "move_operand"
- "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,rO,rK,*d,rK,*c,rO"))]
+ "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"*
{
\"%,mov %0 = %1\",
\"%,mov %0 = %1\",
\"%,mov %0 = %1\",
+ \"%,mov %0 = %1\",
\"mov %0 = pr\",
\"mov pr = %1, -1\"
};
return alt[which_alternative];
}"
- [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,I,M,M,I,I")])
+ [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
""
"addl %0 = @ltoff(@fptr(%1)), gp"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "load_gprel"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
""
"addl %0 = @gprel(%1), gp"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "gprel64_offset"
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
""
"movl %0 = @gprel(%1)"
- [(set_attr "type" "L")])
+ [(set_attr "itanium_class" "long_i")])
(define_expand "load_gprel64"
[(set (match_dup 2)
(plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))]
""
"addl %0 = @ltoff(%1), gp"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word.
emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
DONE;
}"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
;; ??? SSA creates these. Can't allow memories since we don't have
emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
DONE;
}"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
(define_expand "reload_inti"
(%J2) getf.s %0 = %F1
(%J2) setf.s %0 = %1
(%J2) mov %0 = %1"
- [(set_attr "type" "F,M,M,A")
+ [(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
(set_attr "predicable" "no")])
(define_insn "*movsf_internal_astep"
mov %0 = %1
ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0"
- [(set_attr "type" "F,M,M,M,M,A,M,M")
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
(set_attr "predicable" "no")])
(define_insn "*movsf_internal"
mov %0 = %1
ld4%O1 %0 = %1%P1
st4%Q0 %0 = %1%P0"
- [(set_attr "type" "F,M,M,M,M,A,M,M")])
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
(%J2) getf.d %0 = %F1
(%J2) setf.d %0 = %1
(%J2) mov %0 = %1"
- [(set_attr "type" "F,M,M,A")
+ [(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
(set_attr "predicable" "no")])
(define_insn "*movdf_internal_astep"
mov %0 = %1
ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0"
- [(set_attr "type" "F,M,M,M,M,A,M,M")
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
(set_attr "predicable" "no")])
(define_insn "*movdf_internal"
mov %0 = %1
ld8%O1 %0 = %1%P1
st8%Q0 %0 = %1%P0"
- [(set_attr "type" "F,M,M,M,M,A,M,M")])
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word if the variable winds up in GRs.
(match_operand:TF 1 "nonmemory_operand" "fG")))]
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
"(%J2) mov %0 = %F1"
- [(set_attr "type" "F")
+ [(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
(define_insn "*movtf_internal_astep"
mov %0 = %F1
ldfe %0 = %1%P1
stfe %0 = %F1%P0"
- [(set_attr "type" "F,M,M")
+ [(set_attr "itanium_class" "fmisc,fld,stf")
(set_attr "predicable" "no")])
(define_insn "*movtf_internal"
mov %0 = %F1
ldfe %0 = %1%P1
stfe %0 = %F1%P0"
- [(set_attr "type" "F,M,M")])
+ [(set_attr "itanium_class" "fmisc,fld,stf")])
\f
;; ::::::::::::::::::::
;; ::
(sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
""
"sxt1 %0 = %1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "xtd")])
(define_insn "extendhidi2"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
""
"sxt2 %0 = %1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "xtd")])
(define_insn "extendsidi2"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
"@
sxt4 %0 = %1
fsxt.r %0 = %1, %1%B0"
- [(set_attr "type" "I,F")])
+ [(set_attr "itanium_class" "xtd,fmisc")])
;; Unsigned conversions from a smaller integer to a larger integer
"@
zxt1 %0 = %1
ld1%O1 %0 = %1%P1"
- [(set_attr "type" "I,M")])
+ [(set_attr "itanium_class" "xtd,ld")])
(define_insn "zero_extendhidi2"
[(set (match_operand:DI 0 "gr_register_operand" "=r,r")
"@
zxt2 %0 = %1
ld2%O1 %0 = %1%P1"
- [(set_attr "type" "I,M")])
+ [(set_attr "itanium_class" "xtd,ld")])
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
zxt4 %0 = %1
ld4%O1 %0 = %1%P1
fmix.r %0 = f0, %1%B0"
- [(set_attr "type" "I,M,F")])
+ [(set_attr "itanium_class" "xtd,ld,fmisc")])
;; Convert between floating point types of different sizes.
DONE;
}
}"
- [(set_attr "type" "F,F,M,M,M,M")])
+ [(set_attr "itanium_class" "unknown,fmisc,fld,tofr,stf,frfr")])
(define_insn_and_split "extendsftf2"
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
DONE;
}
}"
- [(set_attr "type" "F,F,M,M,M")])
+ [(set_attr "itanium_class" "unknown,fmisc,fld,frfr,stf")])
(define_insn_and_split "extenddftf2"
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
DONE;
}
}"
- [(set_attr "type" "F,F,M,M,M")])
+ [(set_attr "itanium_class" "unknown,fmisc,fld,frfr,stf")])
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fnorm.s %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fnorm.s %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fnorm.d %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
;; Convert between signed integer types and floating point.
(float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xf %0 = %1"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fcvt.fx.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_trunctfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(use (match_operand:SI 2 "const_int_operand" ""))]
""
"fcvt.fx.trunc.s%2 %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
;; Convert between unsigned integer types and floating point.
(unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf.s %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsdidf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf.d %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
""
"fcvt.xuf %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
""
"fcvt.fxu.trunc %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_trunctfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(use (match_operand:SI 2 "const_int_operand" ""))]
""
"fcvt.fxu.trunc.s%2 %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcvtfx")])
\f
;; ::::::::::::::::::::
;; ::
(match_operand:DI 3 "const_int_operand" "n")))]
""
"extr %0 = %1, %3, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
(define_insn "extzv"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 3 "const_int_operand" "n")))]
""
"extr.u %0 = %1, %3, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
;; Insert a bit field.
;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
"(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
|| operands[3] == const0_rtx || operands[3] == constm1_rtx"
"dep %0 = %3, %0, %2, %1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
;; Combine doesn't like to create bitfield insertions into zero.
(define_insn "*depz_internal"
operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
return \"%,dep.z %0 = %1, %2, %3\";
}"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
(define_insn "shift_mix4left"
[(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
(clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
""
"#"
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
(define_split
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
(const_int 32)))]
""
"mix4.l %0 = %0, %r1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "mmshf")])
(define_insn "mix4right"
[(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
(match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
""
"mix4.r %0 = %r1, %0"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "mmshf")])
;; This is used by the rotrsi3 pattern.
(const_int 32))))]
""
"mix4.r %0 = %2, %1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "mmshf")])
\f
;; ::::::::::::::::::::
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
""
- [(set_attr "type" "unknown,I,A")])
+ [(set_attr "itanium_class" "unknown,tbit,ilog")])
(define_insn_and_split "*andcmbi3"
[(set (match_operand:BI 0 "register_operand" "=c,c,r")
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
""
- [(set_attr "type" "unknown,I,A")])
+ [(set_attr "itanium_class" "unknown,tbit,ilog")])
(define_insn_and_split "iorbi3"
[(set (match_operand:BI 0 "register_operand" "=c,c,r")
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
""
- [(set_attr "type" "unknown,I,A")])
+ [(set_attr "itanium_class" "unknown,tbit,ilog")])
(define_insn_and_split "*iorcmbi3"
[(set (match_operand:BI 0 "register_operand" "=c,c")
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
""
- [(set_attr "type" "unknown,I")])
+ [(set_attr "itanium_class" "unknown,tbit")])
(define_insn "one_cmplbi2"
[(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
xor %0 = 1, %1
#
#"
- [(set_attr "type" "I,A,unknown,unknown")])
+ [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
(define_split
[(set (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_and_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C3.and.orcm %0, %I0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_andnot_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_andnot_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C3.or.andcm %I0, %0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_and_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C4.and.orcm %0, %I0 = %3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_and_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C3.and.orcm %0, %I0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_andnot_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C4.or.andcm %I0, %0 = %3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_andnot_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C3.or.andcm %I0, %0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*tbit_and_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.nz.and.orcm %0, %I0 = %1, 0"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_and_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.z.and.orcm %0, %I0 = %1, 0"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_and_2"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.nz.and.orcm %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_and_3"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.z.and.orcm %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*cmpsi_or_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_or_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C3.or.andcm %0, %I0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_orcm_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsi_orcm_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp4.%C3.and.orcm %I0, %0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_or_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C4.or.andcm %0, %I0 = %3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_or_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C3.or.andcm %0, %I0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_orcm_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C4.and.orcm %I0, %0 = %3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_orcm_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 1 "register_operand" "0")))]
""
"cmp.%C3.and.orcm %I0, %0 = r0, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*tbit_or_0"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.nz.or.andcm %0, %I0 = %1, 0"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_or_1"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.z.or.andcm %0, %I0 = %1, 0"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_or_2"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.nz.or.andcm %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*tbit_or_3"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:BI 3 "register_operand" "0")))]
""
"tbit.z.or.andcm %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
;; Transform test of and/or of setcc into parallel comparisons.
(match_operand:HI 2 "gr_register_operand" "r")))]
""
"pmpy2.r %0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "mmmul")])
\f
;; ::::::::::::::::::::
add %0 = %1, %2
adds %0 = %2, %1
addl %0 = %2, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*addsi3_plus1"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(const_int 1)))]
""
"add %0 = %1, %2, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*addsi3_plus1_alt"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(const_int 1)))]
""
"add %0 = %1, %1, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*addsi3_shladd"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 3 "gr_register_operand" "r")))]
""
"shladd %0 = %1, %S2, %3"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 2 "gr_register_operand" "r")))]
""
"sub %0 = %1, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*subsi3_minus1"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 2 "gr_register_operand" "r")))]
""
"sub %0 = %2, %1, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
+
+;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
(define_insn "mulsi3"
[(set (match_operand:SI 0 "fr_register_operand" "=f")
(match_operand:SI 2 "grfr_register_operand" "f")))]
""
"xmpy.l %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
(define_insn "maddsi4"
[(set (match_operand:SI 0 "fr_register_operand" "=f")
(match_operand:SI 3 "grfr_register_operand" "f")))]
""
"xma.l %0 = %1, %2, %3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
(define_insn "negsi2"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
""
"sub %0 = r0, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_expand "abssi2"
[(set (match_dup 2)
add %0 = %1, %2
adds %0 = %2, %1
addl %0 = %2, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*adddi3_plus1"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(const_int 1)))]
""
"add %0 = %1, %2, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; This has some of the same problems as shladd. We let the shladd
;; eliminator hack handle it, which results in the 1 being forced into
(const_int 1)))]
""
"add %0 = %1, %1, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "subdi3"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 2 "gr_register_operand" "r")))]
""
"sub %0 = %1, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_insn "*subdi3_minus1"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 2 "gr_register_operand" "r")))]
""
"sub %0 = %2, %1, 1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; ??? Use grfr instead of fr because of virtual register elimination
;; and silly test cases multiplying by the frame pointer.
(match_operand:DI 2 "grfr_register_operand" "f")))]
""
"xmpy.l %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
;; ??? If operand 3 is an eliminable reg, then register elimination causes the
;; same problem that we have with shladd below. Unfortunately, this case is
(clobber (match_scratch:DI 4 "=X"))]
""
"xma.l %0 = %1, %2, %3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
;; This can be created by register elimination if operand3 of shladd is an
;; eliminable register or has reg_equiv_constant set.
(clobber (match_scratch:DI 5 "=f"))]
"reload_in_progress"
"#"
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
;; ??? Need to emit an instruction group barrier here because this gets split
;; after md_reorg.
(const_int 64))))]
""
"xmpy.h %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(const_int 64))))]
""
"xmpy.hu %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "xmpy")])
(define_insn "negdi2"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
""
"sub %0 = r0, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
(define_expand "absdi2"
[(set (match_dup 2)
(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
""
"popcnt %0 = %1"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "mmmul")])
(define_expand "divdi3"
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fadd.s %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "subsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fsub.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 2 "fr_register_operand" "f")))]
""
"fmpy.s %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fabs %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
""
"fneg %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*nabssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
""
"fnegabs %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "minsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmin %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "maxsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmax %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*maddsf4"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fma.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubsf4"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fms.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmulsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:SF 2 "fr_register_operand" "f"))))]
""
"fnmpy.s %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fnma.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_expand "divsf3"
[(set (match_operand:SF 0 "fr_register_operand" "")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fadd.d %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*adddf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"fadd.s %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "subdf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fsub.d %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*subdf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"fsub.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "muldf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_register_operand" "f")))]
""
"fmpy.d %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*muldf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_register_operand" "f"))))]
""
"fmpy.s %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fabs %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
""
"fneg %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*nabsdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
""
"fnegabs %0 = %1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "mindf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmin %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "maxdf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
"fmax %0 = %1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*madddf4"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fma.d %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*madddf4_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fma.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fms.d %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fms.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_register_operand" "f"))))]
""
"fnmpy.d %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 2 "fr_register_operand" "f")))))]
""
"fnmpy.s %0 = %1, %2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"fnma.d %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.d.s%4 %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"fnma.s %0 = %1, %2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_expand "divdf3"
[(set (match_operand:DF 0 "fr_register_operand" "")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fadd %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*addtf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fadd.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*addtf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fadd.d %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "subtf3"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fsub %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*subtf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fsub.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*subtf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fsub.d %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "multf3"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmpy %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fmpy.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fmpy.d %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_alts"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.s%3 %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncsf_alts"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.s.s%3 %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*multf3_truncdf_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(use (match_operand:SI 3 "const_int_operand" ""))]
""
"fmpy.d.s%3 %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
""
"fabs %0 = %F1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
""
"fneg %0 = %F1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
""
"fnegabs %0 = %F1%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "mintf3"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmin %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "maxtf3"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
""
"fmax %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmisc")])
(define_insn "*maddtf4"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fma %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fma.s %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fma.d %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_alts"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fma.s%4 %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*maddtf4_alts_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fma.d.s%4 %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fms %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fms.s %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*msubtf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fms.d %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
""
"fnmpy %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
""
"fnmpy.s %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmultf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
""
"fnmpy.d %0 = %F1, %F2%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
""
"fnma %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fnma.s %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
""
"fnma.d %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_alts"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.s%4 %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddtf4_truncdf_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fmac")])
(define_expand "divtf3"
[(set (match_operand:TF 0 "fr_register_operand" "")
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"frcpa.s%4 %0, %1 = %2, %3"
- [(set_attr "type" "F")
+ [(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
\f
;; ::::::::::::::::::::
shladd %0 = %1, %2, r0
dep.z %0 = %1, %2, %E2
shl %0 = %1, %2"
- [(set_attr "type" "A,I,I")])
+ [(set_attr "itanium_class" "ialu,ishf,mmshf")])
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "gr_register_operand" "")
;; ::::::::::::::::::::
(define_insn "ashldi3"
- [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
- (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r")
- (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,rM")))]
+ [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
+ (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
+ (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
""
"@
shladd %0 = %1, %2, r0
+ shl %0 = %1, %2
shl %0 = %1, %2"
- [(set_attr "type" "A,I")])
+ [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
;; ??? Maybe combine this with the multiply and add instruction?
(match_operand:DI 3 "gr_register_operand" "r")))]
""
"shladd %0 = %1, %S2, %3"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; This can be created by register elimination if operand3 of shladd is an
;; eliminable register or has reg_equiv_constant set.
(match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
""
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
(define_insn "ashrdi3"
- [(set (match_operand:DI 0 "gr_register_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
- (match_operand:DI 2 "gr_reg_or_6bit_operand" "rM")))]
+ [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
+ (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
+ (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
""
- "shr %0 = %1, %2"
- [(set_attr "type" "I")])
+ "@
+ shr %0 = %1, %2
+ shr %0 = %1, %2"
+ [(set_attr "itanium_class" "mmshf,mmshfi")])
(define_insn "lshrdi3"
- [(set (match_operand:DI 0 "gr_register_operand" "=r")
- (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
- (match_operand:DI 2 "gr_reg_or_6bit_operand" "rM")))]
+ [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
+ (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
+ (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
""
- "shr.u %0 = %1, %2"
- [(set_attr "type" "I")])
+ "@
+ shr.u %0 = %1, %2
+ shr.u %0 = %1, %2"
+ [(set_attr "itanium_class" "mmshf,mmshfi")])
;; Using a predicate that accepts only constants doesn't work, because optabs
;; will load the operand into a register and call the pattern if the predicate
(match_operand:DI 2 "shift_count_operand" "M")))]
""
"shrp %0 = %1, %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
(define_expand "rotldi3"
[(set (match_operand:DI 0 "gr_register_operand" "")
(match_operand:DI 2 "shift_count_operand" "M")))]
""
"shrp %0 = %1, %1, %e2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "ishf")])
\f
;; ::::::::::::::::::::
;; ::
(not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
""
"andcm %0 = -1, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ilog")])
\f
;; ::::::::::::::::::::
;; ::
"@
and %0 = %2, %1
fand %0 = %2, %1%B0"
- [(set_attr "type" "A,F")])
+ [(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "*andnot"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
"@
andcm %0 = %2, %1
fandcm %0 = %2, %1%B0"
- [(set_attr "type" "A,F")])
+ [(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
"@
or %0 = %2, %1
for %0 = %2, %1%B0"
- [(set_attr "type" "A,F")])
+ [(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
"@
xor %0 = %2, %1
fxor %0 = %2, %1%B0"
- [(set_attr "type" "A,F")])
+ [(set_attr "itanium_class" "ilog,fmisc")])
(define_insn "one_cmpldi2"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
""
"andcm %0 = -1, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ilog")])
\f
;; ::::::::::::::::::::
;; ::
(match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
""
"cmp4.%C1 %0, %I0 = %3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
;; We use %r3 because it is possible for us to match a 0, and two of the
;; unsigned comparisons don't accept immediate operands of zero.
(match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
""
"cmp4.%C1 %0, %I0 = %r3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpdi_normal"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
""
"cmp.%C1 %0, %I0 = %3, %r2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
;; We use %r3 because it is possible for us to match a 0, and two of the
;; unsigned comparisons don't accept immediate operands of zero.
(match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
""
"cmp.%C1 %0, %I0 = %r3, %2"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "icmp")])
(define_insn "*cmpsf_internal"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
""
"fcmp.%D1 %0, %I0 = %F2, %F3"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcmp")])
(define_insn "*cmpdf_internal"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
""
"fcmp.%D1 %0, %I0 = %F2, %F3"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcmp")])
(define_insn "*cmptf_internal"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
""
"fcmp.%D1 %0, %I0 = %F2, %F3"
- [(set_attr "type" "F")])
+ [(set_attr "itanium_class" "fcmp")])
;; ??? Can this pattern be generated?
(const_int 0)))]
""
"tbit.z %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
(define_insn "*bit_one"
[(set (match_operand:BI 0 "register_operand" "=c")
(const_int 0)))]
""
"tbit.nz %0, %I0 = %1, %2"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "tbit")])
\f
;; ::::::::::::::::::::
;; ::
(pc)))]
""
"(%J0) br.cond%+ %l2"
- [(set_attr "type" "B")
+ [(set_attr "itanium_class" "br")
(set_attr "predicable" "no")])
(define_insn "*br_false"
(label_ref (match_operand 2 "" ""))))]
""
"(%j0) br.cond%+ %l2"
- [(set_attr "type" "B")
+ [(set_attr "itanium_class" "br")
(set_attr "predicable" "no")])
\f
;; ::::::::::::::::::::
(plus:DI (match_dup 0) (const_int -1))))]
""
"br.cloop.sptk.few %l1"
- [(set_attr "type" "B")
+ [(set_attr "itanium_class" "br")
(set_attr "predicable" "no")])
\f
;; ::::::::::::::::::::
(cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 0)))]
""
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
(define_insn_and_split "*seq_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 1)))]
""
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
\f
;; ::::::::::::::::::::
;; ::
(match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
""
"#"
- [(set_attr "type" "A,unknown")
+ [(set_attr "itanium_class" "ialu,unknown")
(set_attr "predicable" "no")])
(define_split
(match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
""
"#"
- [(set_attr "type" "A,unknown")
+ [(set_attr "itanium_class" "ialu,unknown")
(set_attr "predicable" "no")])
(define_split
}")
(define_insn "call_nopic"
- [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
+ [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(match_operand 1 "" ""))
- (clobber (match_operand:DI 2 "register_operand" "=b"))]
+ (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
""
"br.call%+.many %2 = %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br,scall")])
(define_insn "call_value_nopic"
[(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "call_operand" "bi"))
+ (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
(match_operand 2 "" "")))
- (clobber (match_operand:DI 3 "register_operand" "=b"))]
+ (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
""
"br.call%+.many %3 = %1"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br,scall")])
(define_insn "sibcall_nopic"
- [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
+ [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(match_operand 1 "" ""))
- (use (match_operand:DI 2 "register_operand" "=b"))]
+ (use (match_operand:DI 2 "register_operand" "=b,b"))]
""
"br%+.many %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br,scall")])
(define_insn "call_pic"
- [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
+ [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(match_operand 1 "" ""))
(use (unspec [(reg:DI 1)] 9))
- (clobber (match_operand:DI 2 "register_operand" "=b"))]
+ (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
""
"br.call%+.many %2 = %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br,scall")])
(define_insn "call_value_pic"
[(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "call_operand" "bi"))
+ (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
(match_operand 2 "" "")))
(use (unspec [(reg:DI 1)] 9))
- (clobber (match_operand:DI 3 "register_operand" "=b"))]
+ (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
""
"br.call%+.many %3 = %1"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br,scall")])
(define_insn "sibcall_pic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
(use (match_operand:DI 2 "register_operand" "=b"))]
""
"br%+.many %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
(define_insn "return_internal"
[(return)
(use (match_operand:DI 0 "register_operand" "b"))]
""
"br.ret.sptk.many %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
(define_insn "return"
[(return)]
"ia64_direct_return ()"
"br.ret.sptk.many rp"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
(define_insn "*return_true"
[(set (pc)
(pc)))]
"ia64_direct_return ()"
"(%J0) br.ret%+.many rp"
- [(set_attr "type" "B")
+ [(set_attr "itanium_class" "br")
(set_attr "predicable" "no")])
(define_insn "*return_false"
(return)))]
"ia64_direct_return ()"
"(%j0) br.ret%+.many rp"
- [(set_attr "type" "B")
+ [(set_attr "itanium_class" "br")
(set_attr "predicable" "no")])
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
""
"br %l0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
(define_insn "indirect_jump"
[(set (pc) (match_operand:DI 0 "register_operand" "b"))]
""
"br %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
(define_expand "tablejump"
[(match_operand:DI 0 "register_operand" "")
(use (label_ref (match_operand 1 "" "")))]
""
"br %0"
- [(set_attr "type" "B")])
+ [(set_attr "itanium_class" "br")])
\f
;; ::::::::::::::::::::
add %0 = %1, %2
adds %0 = %2, %1
addl %0 = %2, %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; This prevents the scheduler from moving the SP restore past FP-relative
;; stack accesses. This is similar to movdi plus the extra set.
(set (match_dup 1) (match_dup 1))]
""
"mov %0 = %1"
- [(set_attr "type" "A")])
+ [(set_attr "itanium_class" "ialu")])
;; Allocate a new register frame.
(use (match_operand:DI 4 "const_int_operand" "i"))]
""
"alloc %0 = ar.pfs, %1, %2, %3, %4"
- [(set_attr "type" "M")
+ [(set_attr "itanium_class" "syst_m0")
(set_attr "predicable" "no")])
;; Modifies ar.unat
(clobber (match_operand:DI 3 "register_operand" ""))]
""
".mem.offset %2, 0\;st8.spill %0 = %1%P0"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "st")])
;; Reads ar.unat
(define_expand "gr_restore"
(use (match_operand:DI 3 "register_operand" ""))]
""
".mem.offset %2, 0\;ld8.fill %0 = %1%P1"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "ld")])
(define_insn "fr_spill"
[(set (match_operand:TF 0 "memory_operand" "=m")
(unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))]
""
"stf.spill %0 = %1%P0"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "stf")])
(define_insn "fr_restore"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))]
""
"ldf.fill %0 = %1%P1"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "fld")])
(define_insn "bsp_value"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] 20))]
""
"mov %0 = ar.bsp"
- [(set_attr "type" "I")])
+ [(set_attr "itanium_class" "frar_i")])
(define_insn "set_bsp"
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)]
""
"flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
(define_insn "flushrs"
[(unspec [(const_int 0)] 21)]
""
";;\;flushrs"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "rse_m")])
\f
;; ::::::::::::::::::::
;; ::
[(const_int 0)]
""
"nop 0"
- [(set_attr "type" "unknown")])
+ [(set_attr "itanium_class" "unknown")])
;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
[(unspec_volatile [(const_int 0)] 1)]
""
""
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "insn_group_barrier"
[(unspec_volatile [(const_int 0)] 2)]
""
";;"
- [(set_attr "type" "S")
+ [(set_attr "itanium_class" "stop_bit")
(set_attr "predicable" "no")])
\f
(unspec:BLK [(match_operand:BLK 1 "" "")] 12))]
""
"mf"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "syst_m")])
(define_insn "fetchadd_acq_si"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 2 "fetchadd_operand" "n")] 19))]
""
"fetchadd4.acq %0 = %1, %2"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
(define_insn "fetchadd_acq_di"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 2 "fetchadd_operand" "n")] 19))]
""
"fetchadd8.acq %0 = %1, %2"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
(define_insn "cmpxchg_acq_si"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
""
"cmpxchg4.acq %0 = %1, %2, %3"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
(define_insn "cmpxchg_acq_di"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
""
"cmpxchg8.acq %0 = %1, %2, %3"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
(define_insn "xchgsi"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(match_operand:SI 2 "gr_register_operand" "r"))]
""
"xchg4 %0 = %1, %2"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
(define_insn "xchgdi"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(match_operand:DI 2 "gr_register_operand" "r"))]
""
"xchg8 %0 = %1, %2"
- [(set_attr "type" "M")])
+ [(set_attr "itanium_class" "sem")])
\f
;; Predication.
(unspec:BI [(match_dup 0)] 7))]
""
".pred.rel.mutex %0, %I0"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "safe_across_calls_all"
[(unspec_volatile [(const_int 0)] 8)]
""
".pred.safe_across_calls p1-p63"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "safe_across_calls_normal"
emit_safe_across_calls (asm_out_file);
return \"\";
}"
- [(set_attr "type" "unknown")
+ [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
projects / platform / upstream / linaro-gcc.git / commitdiff