drm/i915/dvo/sil164: Fix suspend/resume

Poke a few more bits into the SiI164 to make it
recover after S3. HEN/VEN are the important bits,
the rest PLL filter/HPD detection I just did
for good measure to match the BIOS programming.

Note that the spec recommended SCNT bit in REGC
isn't set by the BIOS at least for me, so I left
it out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-4-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c
index 32dd3b9..4acc8ce 100644 (file)
--- a/drivers/gpu/drm/i915/display/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/display/dvo_sil164.c
@@ -58,6 +58,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define SIL164_9_MDI (1<<0)
 
 #define SIL164_REGC 0x0c
+#define SIL164_C_SCNT (1<<7)
+#define SIL164_C_PLLF_MASK (0xf<<1)
+#define SIL164_C_PLLF_REC (4<<1)
+#define SIL164_C_PFEN (1<<0)
 
 struct sil164_priv {
        //I2CDevRec d;
@@ -205,6 +209,13 @@ static void sil164_mode_set(struct intel_dvo_device *dvo,
          sil164_writeb(sil, 0x0c, 0x89);
          sil164_writeb(sil, 0x08, 0x31);*/
        /* don't do much */
+
+       sil164_writeb(dvo, SIL164_REG8,
+                     SIL164_8_VEN | SIL164_8_HEN);
+       sil164_writeb(dvo, SIL164_REG9,
+                     SIL164_9_TSEL);
+       sil164_writeb(dvo, SIL164_REGC,
+                     SIL164_C_PLLF_REC | SIL164_C_PFEN);
 }
 
 /* set the SIL164 power state */