#define VME_A64_MAX 0x10000000000000000ULL
#define VME_CRCSR_MAX 0x1000000ULL
-
/* VME Cycle Types */
#define VME_SCT 0x1
#define VME_BLT 0x2
int vme_register_driver(struct vme_driver *, unsigned int);
void vme_unregister_driver(struct vme_driver *);
-
#endif /* _VME_H_ */
return 0;
}
-
static int fake_master_get(struct vme_master_resource *image, int *enabled,
unsigned long long *vme_base, unsigned long long *size,
u32 *aspace, u32 *cycle, u32 *dwidth)
return retval;
}
-
static void fake_lm_check(struct fake_driver *bridge, unsigned long long addr,
u32 aspace, u32 cycle)
{
kfree(bridge->crcsr_kernel);
}
-
static int __init fake_init(void)
{
int retval, i;
}
-
static void __exit fake_exit(void)
{
struct list_head *pos = NULL;
root_device_unregister(vme_root);
}
-
MODULE_PARM_DESC(geoid, "Set geographical addressing");
module_param(geoid, int, 0);
static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
static void tsi148_remove(struct pci_dev *);
-
/* Module parameter */
static bool err_chk;
static int geoid;
/* Need granularity before we set the size */
*size = (unsigned long long)((vme_bound - *vme_base) + granularity);
-
if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
*cycle |= VME_2eSST160;
if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
return 0;
}
-
static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
u32 *cycle, u32 *dwidth)
return retval;
}
-
static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
size_t count, loff_t offset)
{
if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
*aspace |= VME_A64;
-
if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
*cycle |= VME_SUPER;
if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
bridge = tsi148_bridge->driver_priv;
-
dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
/*
* Control and Status Registers
*/
-
/*
* Command/Status Registers (CRG + $004)
*/
#define TSI148_LCSR_IT7_ITOFL 0x3F4
#define TSI148_LCSR_IT7_ITAT 0x3F8
-
#define TSI148_LCSR_IT0 0x300
#define TSI148_LCSR_IT1 0x320
#define TSI148_LCSR_IT2 0x340
#define TSI148_LCSR_DMA0 0x500
#define TSI148_LCSR_DMA1 0x580
-
static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
TSI148_LCSR_DMA1 };
#define TSI148_CSRBSR 0xFF8
#define TSI148_CBAR 0xFFC
-
-
-
/*
* TSI148 Register Bit Definitions
*/
#define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */
#define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */
-
/*
* VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
*/