Documentation:devicetree:clock:Add starfive clock yaml

Add starfive clkgen, vout and isp yaml file.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml
new file mode 100755 (executable)
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--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clk-isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 ISP Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clk-isp
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DVP clock
+      - description: ISP CORE_2X clock
+      - description: ISP AXI clock
+      - description: NOC_BUS ISP clock
+
+  clock-names:
+    items:
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_dvp
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi
+      - const: u0_sft7110_noc_bus_clk_isp_axi
+
+  resets:
+    items:
+      - description: ISP reset
+      - description: ISP AXI reset
+      - description: NOC_BUS ISP reset
+
+  reset-names:
+    items:
+      - const: rst_isp_top_n
+      - const: rst_isp_top_axi
+      - const: rst_isp_noc_bus_n
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-clk-isp.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      ISP domain power
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - '#clock-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/clock/starfive-jh7110-clk-isp.h>
+    clkisp: clock-controller@19810000 {
+        compatible = "starfive,jh7110-clk-isp";
+        reg = <0x0 0x19810000 0x0 0x10000>;
+        reg-names = "isp";
+        #clock-cells = <1>;
+        clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
+                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
+        clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+                      "u0_sft7110_noc_bus_clk_isp_axi";
+        resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
+                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
+        reset-names = "rst_isp_top_n", "rst_isp_top_axi",
+                      "rst_isp_noc_bus_n";
+        power-domains = <&pwrc JH7110_PD_ISP>;
+    };

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-vout.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-vout.yaml
new file mode 100755 (executable)
index 0000000..2e10956
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-vout.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clk-vout.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 VOUT Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clk-vout
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: external HDMI clock
+      - description: external MIPI Escape mode Receive clock
+      - description: external MIPI high-speed Transmit clock
+      - description: VOUT SRC clock
+      - description: VOUT AHB clock
+
+  clock-names:
+    items:
+      - const: hdmitx0_pixelclk
+      - const: mipitx_dphy_rxesc
+      - const: mipitx_dphy_txbytehs
+      - const: vout_src
+      - const: vout_top_ahb
+
+  resets:
+    items:
+      - description: VOUT SRC reset
+
+  reset-names:
+    items:
+      - const: vout_src
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-vout.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      VOUT domain power
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - '#clock-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/clock/starfive-jh7110-vout.h>
+    clkvout: clock-controller@295C0000 {
+        compatible = "starfive,jh7110-clk-vout";
+        reg = <0x0 0x295C0000 0x0 0x10000>;
+        reg-names = "vout";
+        clocks = <&hdmitx0_pixelclk>,
+                 <&mipitx_dphy_rxesc>,
+                 <&mipitx_dphy_txbytehs>,
+                 <&clkgen JH7110_VOUT_SRC>,
+                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
+        clock-names = "hdmitx0_pixelclk",
+                      "mipitx_dphy_rxesc",
+                      "mipitx_dphy_txbytehs",
+                      "vout_src",
+                      "vout_top_ahb";
+        resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
+        reset-names = "vout_src";
+        #clock-cells = <1>;
+        power-domains = <&pwrc JH7110_PD_VOUT>;
+    };

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen.yaml
new file mode 100755 (executable)
index 0000000..a928b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clkgen
+
+  reg:
+    maxItems: 3
+
+  clocks:
+    items:
+      - description: Main clock source
+      - description: external RMII clock for GMAC1
+      - description: external RGMII clock for GMAC1
+      - description: I2S Transmit serial clock
+      - description: I2S Transmit frame sync clock
+      - description: I2S Receive serial clock
+      - description: I2S Receive frame sync clock
+      - description: external TDM clock
+      - description: external Master clock
+      - description: inner JTAG TCK clock
+      - description: BIST clock
+      - description: RTC clock
+      - description: external RMII clock for GMAC0
+      - description: external RGMII clock for GMAC0
+
+  clock-names:
+    items:
+      - const: osc
+      - const: gmac1_rmii_refin
+      - const: gmac1_rgmii_rxin
+      - const: i2stx_bclk_ext
+      - const: i2stx_lrck_ext
+      - const: i2srx_bclk_ext
+      - const: i2srx_lrck_ext
+      - const: tdm_ext
+      - const: clk_mclk_ext
+      - const: jtag_tck_inner
+      - const: clk_bist_apb
+      - const: clk_rtc
+      - const: gmac0_rmii_refin
+      - const: gmac0_rgmii_rxin
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-clkgen.h> for valid indices.
+
+  starfive,sys-syscon:
+    description:
+      PLL clock configuration registers.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - starfive,sys-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    clkgen: clock-controller {
+        compatible = "starfive,jh7110-clkgen";
+        reg = <0x0 0x13020000 0x0 0x10000>,
+              <0x0 0x10230000 0x0 0x10000>,
+              <0x0 0x17000000 0x0 0x10000>;
+        reg-names = "sys", "stg", "aon";
+        clocks = <&osc>, <&gmac1_rmii_refin>,
+                 <&gmac1_rgmii_rxin>,
+                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                 <&tdm_ext>, <&mclk_ext>,
+                 <&jtag_tck_inner>, <&bist_apb>,
+                 <&clk_rtc>,
+                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+        clock-names = "osc", "gmac1_rmii_refin",
+                      "gmac1_rgmii_rxin",
+                      "i2stx_bclk_ext", "i2stx_lrck_ext",
+                      "i2srx_bclk_ext", "i2srx_lrck_ext",
+                      "tdm_ext", "mclk_ext",
+                      "jtag_tck_inner", "bist_apb",
+                      "clk_rtc",
+                      "gmac0_rmii_refin", "gmac0_rgmii_rxin";
+        #clock-cells = <1>;
+        starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+                  0x20 0x24 0x28 0x2c 0x30 0x34>;
+    };