F: drivers/net/ethernet/broadcom/b44.*
BROADCOM B53/SF2 ETHERNET SWITCH DRIVER
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
L: netdev@vger.kernel.org
L: openwrt-devel@lists.openwrt.org (subscribers-only)
S: Supported
F: include/linux/platform_data/b53.h
BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
N: raspberrypi
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
M: Ray Jui <rjui@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
BROADCOM BCM5301X ARM ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
F: arch/arm/mach-bcm/bcm_5301x.c
BROADCOM BCM53573 ARM ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
M: Rafał Miłecki <rafal@milecki.pl>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
F: drivers/usb/gadget/udc/bcm63xx_udc.*
BROADCOM BCM7XXX ARM ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
M: William Zhang <william.zhang@broadcom.com>
M: Anand Gore <anand.gore@broadcom.com>
M: Kursad Oney <kursad.oney@broadcom.com>
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
M: Rafał Miłecki <rafal@milecki.pl>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
N: bcm[9]?6878
BROADCOM BDC DRIVER
-M: Justin Chen <justinpopo6@gmail.com>
+M: Justin Chen <justin.chen@broadcom.com>
M: Al Cooper <alcooperx@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-usb@vger.kernel.org
F: drivers/cpufreq/bmips-cpufreq.c
BROADCOM BMIPS MIPS ARCHITECTURE
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-mips@vger.kernel.org
S: Maintained
BROADCOM BRCMSTB GPIO DRIVER
M: Doug Berger <opendmb@gmail.com>
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
S: Supported
F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
F: drivers/gpio/gpio-brcmstb.c
BROADCOM BRCMSTB I2C DRIVER
-M: Kamal Dasu <kdasu.kdev@gmail.com>
+M: Kamal Dasu <kamal.dasu@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-i2c@vger.kernel.org
S: Supported
F: drivers/tty/serial/8250/8250_bcm7271.c
BROADCOM BRCMSTB USB EHCI DRIVER
-M: Justin Chen <justinpopo6@gmail.com>
+M: Justin Chen <justin.chen@broadcom.com>
M: Al Cooper <alcooperx@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-usb@vger.kernel.org
F: drivers/usb/misc/brcmstb-usb-pinmap.c
BROADCOM BRCMSTB USB2 and USB3 PHY DRIVER
-M: Justin Chen <justinpopo6@gmail.com>
+M: Justin Chen <justin.chen@broadcom.com>
M: Al Cooper <alcooperx@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-kernel@vger.kernel.org
F: drivers/spi/spi-bcmbca-hsspi.c
BROADCOM ETHERNET PHY DRIVERS
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
BROADCOM GENET ETHERNET DRIVER
M: Doug Berger <opendmb@gmail.com>
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER
M: Rafał Miłecki <rafal@milecki.pl>
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-pm@vger.kernel.org
S: Maintained
F: include/linux/bcma/
BROADCOM SPI DRIVER
-M: Kamal Dasu <kdasu.kdev@gmail.com>
+M: Kamal Dasu <kamal.dasu@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
S: Maintained
F: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
BROADCOM STB NAND FLASH DRIVER
M: Brian Norris <computersforpeace@gmail.com>
-M: Kamal Dasu <kdasu.kdev@gmail.com>
+M: Kamal Dasu <kamal.dasu@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-mtd@lists.infradead.org
S: Maintained
BROADCOM STB PCIE DRIVER
M: Jim Quinlan <jim2101024@gmail.com>
M: Nicolas Saenz Julienne <nsaenz@kernel.org>
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: drivers/pci/controller/pcie-brcmstb.c
BROADCOM SYSTEMPORT ETHERNET DRIVER
-M: Florian Fainelli <f.fainelli@gmail.com>
+M: Florian Fainelli <florian.fainelli@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
K: \bTIF_SECCOMP\b
SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) Broadcom BRCMSTB DRIVER
-M: Kamal Dasu <kdasu.kdev@gmail.com>
+M: Kamal Dasu <kamal.dasu@broadcom.com>
M: Al Cooper <alcooperx@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-mmc@vger.kernel.org
/*
* Configure the SA1111 shared memory controller.
*/
-void
+static void
sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
unsigned int cas_latency)
{
#include <linux/etherdevice.h>
#include <linux/davinci_emac.h>
#include <linux/dma-mapping.h>
+#include <linux/platform_data/davinci-cpufreq.h>
#include <asm/tlb.h>
#include <asm/mach/map.h>
extern void davinci_init_ide(void);
void davinci_init_late(void);
-#ifdef CONFIG_CPU_FREQ
-int davinci_cpufreq_init(void);
-#else
-static inline int davinci_cpufreq_init(void) { return 0; }
-#endif
-
#ifdef CONFIG_SUSPEND
int davinci_pm_init(void);
#else
#include <linux/io.h>
#include <asm/mach/time.h>
#include "soc.h"
+#include "platform.h"
/*************************************************************************
* Timer handling for EP93xx
return ret;
}
-u64 ep93xx_clocksource_read(struct clocksource *c)
+static u64 ep93xx_clocksource_read(struct clocksource *c)
{
u64 ret;
default y
depends on ARCH_EXYNOS4
+config SOC_EXYNOS4212
+ bool "Samsung Exynos4212"
+ default y
+ depends on ARCH_EXYNOS4
+
config SOC_EXYNOS4412
bool "Samsung Exynos4412"
default y
#define EXYNOS3_SOC_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
+#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos4210() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212() is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS4412)
# define soc_is_exynos4412() is_samsung_exynos4412()
#else
exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
#endif
if (of_machine_is_compatible("samsung,exynos4210") ||
+ of_machine_is_compatible("samsung,exynos4212") ||
(of_machine_is_compatible("samsung,exynos4412") &&
(of_machine_is_compatible("samsung,trats2") ||
of_machine_is_compatible("samsung,midas") ||
"samsung,exynos3250",
"samsung,exynos4",
"samsung,exynos4210",
+ "samsung,exynos4212",
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
*
* On Exynos5 devices the call is ignored by trustzone firmware.
*/
- if (!soc_is_exynos4210() && !soc_is_exynos4412())
+ if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
+ !soc_is_exynos4412())
return 0;
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
+ * But, Exynos4212 has only one secondary CPU so second parameter
+ * isn't used for informing secure firmware about CPU id.
*/
+ if (soc_is_exynos4212())
+ cpu = 0;
+
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
exynos_pm_central_suspend();
- if (soc_is_exynos4412()) {
+ if (soc_is_exynos4212() || soc_is_exynos4412()) {
/* Setting SEQ_OPTION register */
pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
S5P_CENTRAL_SEQ_OPTION);
EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
+EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
.compatible = "samsung,exynos4210-pmu",
.data = &exynos4_pm_data,
}, {
+ .compatible = "samsung,exynos4212-pmu",
+ .data = &exynos4_pm_data,
+ }, {
.compatible = "samsung,exynos4412-pmu",
.data = &exynos4_pm_data,
}, {
#include <uapi/linux/psci.h>
+#include "core.h"
+
#define HIGHBANK_SUSPEND_PARAM \
((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
+#include "common.h"
static int imx25_suspend_enter(suspend_state_t state)
{
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/soc/nxp/lpc32xx-misc.h>
#include "lpc32xx.h"
#include "common.h"
error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
if (error)
- printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
+ pr_err("sysfs_create_file failed: %d\n", error);
if (cpu_is_omap16xx()) {
/* configure LOW_PWR pin */
#include <asm/mach-types.h>
+#include "common.h"
#include "serial.h"
#include "mux.h"
#include "pm.h"
#define OMAP1_SRAM_PA 0x20000000
#define SRAM_BOOTLOADER_SZ 0x80
-#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
+#define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
static void __iomem *omap_sram_base;
static unsigned long omap_sram_start;
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
"vsd", 1, GPIO_ACTIVE_HIGH),
/* Slot index 1, VIO power, GPIO 9 */
GPIO_LOOKUP_IDX("gpio-0-15", 9,
- "vsd", 1, GPIO_ACTIVE_HIGH),
+ "vio", 1, GPIO_ACTIVE_HIGH),
{ }
},
};
static void irq_save_secure_context(void)
{
u32 ret;
+
ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
- .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4,
},
},
/*
* According to Mark Greer, the MPU will not return from WFI
* when the EMAC signals an interrupt.
- * http://www.spinics.net/lists/arm-kernel/msg174734.html
+ * https://lore.kernel.org/all/1336770778-23044-3-git-send-email-mgreer@animalcreek.com/
*/
.flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
};
NULL
};
-
/*
* Apparently the SHA/MD5 and AES accelerator IP blocks are
* only present on some AM35xx chips, and no one knows which
- * ones. See
- * http://www.spinics.net/lists/arm-kernel/msg215466.html So
- * if you need these IP blocks on an AM35xx, try uncommenting
+ * ones.
+ * See https://lore.kernel.org/all/20130108203853.GB1876@animalcreek.com/
+ * So if you need these IP blocks on an AM35xx, try uncommenting
* the following lines.
*/
static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * This file configures the internal USB PHY in OMAP4430. Used
- * with TWL6030 transceiver and MUSB on OMAP4430.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
- * Author: Hema HK <hemahk@ti.com>
- */
+ * This file configures the internal USB PHY in OMAP4430. Used
+ * with TWL6030 transceiver and MUSB on OMAP4430.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
+ * Author: Hema HK <hemahk@ti.com>
+ */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
// SPDX-License-Identifier: GPL-2.0-only
/*
- * linux/arch/arm/mach-omap2/sdrc2xxx.c
- *
* SDRAM timing related functions for OMAP2xxx
*
* Copyright (C) 2005, 2008 Texas Instruments Inc.
#define GP_DEVICE 0x300
-#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
+#define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
static unsigned long omap_sram_start;
static unsigned long omap_sram_size;
*/
static int is_sram_locked(void)
{
- if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
+ if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) {
writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
{
omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, 0,
TI81XX_PRM_DEVICE_RSTCTRL);
- while (1);
+ while (1)
+ ;
}
if (of_machine_is_compatible("maxtor,shared-storage-2"))
mss2_init();
+ if (of_machine_is_compatible("lacie,d2-network"))
+ d2net_init();
+
of_platform_default_populate(NULL, orion5x_auxdata_lookup, NULL);
}
static inline void mss2_init(void) {}
#endif
+#ifdef CONFIG_MACH_D2NET_DT
+void d2net_init(void);
+#else
+static inline void d2net_init(void) {}
+#endif
+
/*****************************************************************************
* Helpers to access Orion registers
****************************************************************************/
extern void __init pxa26x_init_irq(void);
#define pxa27x_handle_irq ichp_handle_irq
-extern unsigned pxa27x_get_clk_frequency_khz(int);
extern void __init pxa27x_init_irq(void);
extern void __init pxa27x_map_io(void);
static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
#endif
-/*
- * Once fully converted to the clock framework, all these functions should be
- * removed, and replaced with a clk_get(NULL, "core").
- */
-#ifdef CONFIG_PXA25x
-extern unsigned pxa25x_get_clk_frequency_khz(int);
-#else
-#define pxa25x_get_clk_frequency_khz(x) (0)
-#endif
-
-#ifdef CONFIG_PXA27x
-#else
-#define pxa27x_get_clk_frequency_khz(x) (0)
-#endif
#include "pxa2xx-regs.h"
#include "mfp-pxa2xx.h"
+#include "mfp-pxa27x.h"
#include "generic.h"
#include <linux/irqchip.h>
#include <linux/platform_data/mmp_dma.h>
#include <linux/soc/pxa/cpu.h>
+#include <linux/soc/pxa/smemc.h>
#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <linux/platform_data/i2c-pxa.h>
#include <linux/platform_data/mmp_dma.h>
#include <linux/soc/pxa/cpu.h>
+#include <linux/soc/pxa/smemc.h>
#include <asm/mach/map.h>
#include <asm/irq.h>
#include "irqs.h"
#include "pxa27x.h"
#include "reset.h"
+#include <linux/platform_data/pxa2xx_udc.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/asoc-pxa.h>
#include "pm.h"
#include "addr-map.h"
#include "smemc.h"
#include "regs-ost.h"
#include "reset.h"
#include "smemc.h"
+#include "generic.h"
static void do_hw_reset(void);
gpio_get_value(SPITZ_GPIO_SYNC);
}
-unsigned long spitzpm_read_devdata(int type)
+static unsigned long spitzpm_read_devdata(int type)
{
switch (type) {
case SHARPSL_STATUS_ACIN:
help
Common setup code for i2c bus 1.
-config S3C64XX_SETUP_IDE
- bool
- help
- Common setup code for S3C64XX IDE.
-
config S3C64XX_SETUP_FB_24BPP
bool
help
select S3C64XX_DEV_SPI0
select S3C64XX_SETUP_FB_24BPP
select S3C64XX_SETUP_I2C1
- select S3C64XX_SETUP_IDE
select S3C64XX_SETUP_KEYPAD
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_SPI
.driver = {
.name = "wlf-gf-module"
},
- .probe_new = wlf_gf_module_probe,
+ .probe = wlf_gf_module_probe,
.id_table = wlf_gf_module_id,
};
sa1100_register_uart(2, 3);
}
-void __init assabet_init_irq(void)
+static void __init assabet_init_irq(void)
{
u32 def_val;
#include <asm/suspend.h>
#include <asm/mach/time.h>
+#include "generic.h"
+
extern int sa1100_finish_suspend(unsigned long);
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#include <linux/spinlock_types.h>
#include "spear.h"
#include "misc_regs.h"
+#include "pl080.h"
static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
static void __iomem *versatile_sys_base;
-unsigned int mmc_status(struct device *dev)
+static unsigned int mmc_status(struct device *dev)
{
struct amba_device *adev = container_of(dev, struct amba_device, dev);
u32 mask;
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
+#include <linux/clk/pxa.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/soc/pxa/smemc.h>
+#include <linux/soc/pxa/cpu.h>
#include <dt-bindings/clock/pxa-clock.h>
#include "clk-pxa.h"
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/soc/pxa/smemc.h>
+#include <linux/clk/pxa.h>
#include <dt-bindings/clock/pxa-clock.h>
#include "clk-pxa.h"
return (unsigned int)clks[0] / KHz;
}
-bool pxa27x_is_ppll_disabled(void)
+static bool pxa27x_is_ppll_disabled(void)
{
unsigned long ccsr = readl(clk_regs + CCSR);
#ifdef CONFIG_SHARPSL_PM
static struct max1111_data *the_max1111;
+int max1111_read_channel(int channel);
int max1111_read_channel(int channel)
{
if (!the_max1111 || !the_max1111->spi)
static const struct ads7846_platform_data *ads7846_get_props(struct device *dev)
{
struct ads7846_platform_data *pdata;
- const struct platform_device_id *pdev_id;
u32 value;
- pdev_id = device_get_match_data(dev);
- if (!pdev_id) {
- dev_err(dev, "Unknown device model\n");
- return ERR_PTR(-EINVAL);
- }
-
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
- pdata->model = (unsigned long)pdev_id->driver_data;
+ pdata->model = (uintptr_t)device_get_match_data(dev);
device_property_read_u16(dev, "ti,vref-delay-usecs",
&pdata->vref_delay_usecs);
udc_disable(udc);
}
-#ifdef CONFIG_PXA27x
-extern void pxa27x_clear_otgph(void);
-#else
-#define pxa27x_clear_otgph() do {} while (0)
-#endif
-
#ifdef CONFIG_PM
/**
* pxa_udc_suspend - Suspend udc device
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
+#include <linux/platform_data/pxa2xx_udc.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/signal.h>
__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
}
-#ifdef CONFIG_PXA27x
-extern void pxa27x_clear_otgph(void);
-#else
-#define pxa27x_clear_otgph() do {} while (0)
-#endif
-
static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
{
int retval;
} pxa2xx_audio_ops_t;
extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
+extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
#endif
int (*init)(void);
};
+#ifdef CONFIG_CPU_FREQ
+int davinci_cpufreq_init(void);
+#else
+static inline int davinci_cpufreq_init(void) { return 0; }
+#endif
+
#endif /* _MACH_DAVINCI_CPUFREQ_H */
int gpio_pullup; /* high == pullup activated */
};
+#ifdef CONFIG_PXA27x
+extern void pxa27x_clear_otgph(void);
+#else
+#define pxa27x_clear_otgph() do {} while (0)
+#endif
+
#endif
unsigned int pxa3xx_smemc_get_memclkdiv(void);
void __iomem *pxa_smemc_get_mdrefr(void);
+/*
+ * Once fully converted to the clock framework, all these functions should be
+ * removed, and replaced with a clk_get(NULL, "core").
+ */
+#ifdef CONFIG_PXA25x
+extern unsigned pxa25x_get_clk_frequency_khz(int);
+#else
+#define pxa25x_get_clk_frequency_khz(x) (0)
+#endif
+
+#ifdef CONFIG_PXA27x
+extern unsigned pxa27x_get_clk_frequency_khz(int);
+#else
+#define pxa27x_get_clk_frequency_khz(x) (0)
+#endif
+
#endif
static int reset_gpio;
static void __iomem *ac97_reg_base;
-extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
-
/*
* Beware PXA27x bugs:
*
projects / platform / kernel / linux-rpi.git / commitdiff